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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-03 16:22:49 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-10 09:50:17 +0000 |
| commit | 0678bea4b6dcd6c3e90ca400fbb5d5ec65f694f4 (patch) | |
| tree | 5171e60ac9b86ddc78e1e525af7d2c46af6f956f /src/mainboard/google/glados/devicetree.cb | |
| parent | 44b01fdcd7bbd7e619f496530d3bfbea69f7fce9 (diff) | |
| download | coreboot-0678bea4b6dcd6c3e90ca400fbb5d5ec65f694f4.tar.gz coreboot-0678bea4b6dcd6c3e90ca400fbb5d5ec65f694f4.tar.bz2 coreboot-0678bea4b6dcd6c3e90ca400fbb5d5ec65f694f4.zip | |
glados: Enable DPTF
- Add ACPI code for DPTF support with placeholder thresholds
- Do not have custom PDL for mainboard
- Do not have enable charger control for DPTF as there is
already a complicated charge profile in the EC. We may still
want to enable this but it would need to be tuned to work
well with the EC profile.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297745
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1d2f8bf16309..60966c7e07ec 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" |