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| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-09 14:45:02 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:39:07 +0200 |
| commit | 3d7020e0c48dcf5a61e68c284759c108907addaf (patch) | |
| tree | f080129249d96a7ffec0b2dd3445df5a14942727 /src/mainboard/google/glados/devicetree.cb | |
| parent | 50ed38feba58ff59248015285bfdbe1c37cc4136 (diff) | |
| download | coreboot-3d7020e0c48dcf5a61e68c284759c108907addaf.tar.gz coreboot-3d7020e0c48dcf5a61e68c284759c108907addaf.tar.bz2 coreboot-3d7020e0c48dcf5a61e68c284759c108907addaf.zip | |
glados: make EC_SCI_L work
In order for the EC_SCI_L to work the GPE0 route needs
to be set along w/ the GPE event for the EC. As the GPE0
route is dynamic the EC_SCI_GPI needs to be set along
with the route so everything lines up. In this case, the
GPE0 route is set to the defaults such that GPP_C, GPP_D,
and GPP_E are routed to GPE0 block 0, 1, and 2, respectively.
This works out for glados because the EC_SCI_L is connected
to GPP_E16.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts
is incrementing as well as /sys/firmware/acpi/interrupts/gpe50.
Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292011
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11210
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2e1cae75a875..9bb065de1765 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,6 +49,14 @@ chip soc/intel/skylake register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # Embedded Controller host command window register "gen1_dec" = "0x00fc0801" |