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| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-04 11:03:00 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:14:34 +0200 |
| commit | 43b1066c0dd67a3d793298096b661cb6e03f65c4 (patch) | |
| tree | 9edc23e87c4f7e2832b8a76d893de9f60ee60d54 /src/mainboard/google/glados/devicetree.cb | |
| parent | a7a57701d6297e1d103d13b48fa98e51148670a3 (diff) | |
| download | coreboot-43b1066c0dd67a3d793298096b661cb6e03f65c4.tar.gz coreboot-43b1066c0dd67a3d793298096b661cb6e03f65c4.tar.bz2 coreboot-43b1066c0dd67a3d793298096b661cb6e03f65c4.zip | |
glados: enable SMBus device
In order to run with the debug FSP the SMBus device needs
to be enabled. Additionally, the TCO block lives within
the SMBus device so if TCO is to be employed then the
SMBus device needs to be enabled as a prerequisite.
BUG=chrome-os-partner:42407
BRANCH=None
TEST=Buit and booted into kernel.
Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290364
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11181
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index b48556f1d5ec..2e1cae75a875 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/skylake register "IshEnable" = "0" register "XdciEnable" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "0" + register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -102,7 +102,7 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio - device pci 1f.4 off end # SMBus Controller + device pci 1f.4 on end # SMBus Controller device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE Controller end |