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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 15:50:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-08-14 10:53:47 +0000 |
| commit | 29e71b1291bd22366d75b4dc3c897b355ff268ce (patch) | |
| tree | 21fe08ac0057cdbf839b0f8a2f9d440e834c6900 /src/mainboard/google/jecht | |
| parent | 2a90e396fc1b0d008024cff1a1b02ee8f1cd0036 (diff) | |
| download | coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.gz coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.bz2 coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.zip | |
broadwell: Move some MRC/refcode settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/jecht')
| -rw-r--r-- | src/mainboard/google/jecht/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/spd/spd.c | 1 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/variants/guado/pei_data.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/variants/jecht/pei_data.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/variants/rikku/pei_data.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/variants/tidus/pei_data.c | 2 |
6 files changed, 2 insertions, 9 deletions
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index e972baabafdf..2f2fa4a44391 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,6 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "dq_pins_interleaved" = "true" + device cpu_cluster 0 on chip cpu/intel/haswell device lapic 0 on end diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 6446a937e1bf..2a9f6b19202d 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -10,5 +10,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; // Enable 2x refresh mode pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; } diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 566b9ad6eeff..558d735864a3 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: Port 3, USB3 */ |