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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-02 08:42:04 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:28:02 +0000 |
| commit | 7bde4e80be27b35abf13114eb8b6096755458d2e (patch) | |
| tree | 041a56125b048885a2aafe34eadd08032d6314c0 /src/mainboard/google/jecht | |
| parent | 9180bae9b2030bb3745c6d4d1e3e1187d7c30089 (diff) | |
| download | coreboot-7bde4e80be27b35abf13114eb8b6096755458d2e.tar.gz coreboot-7bde4e80be27b35abf13114eb8b6096755458d2e.tar.bz2 coreboot-7bde4e80be27b35abf13114eb8b6096755458d2e.zip | |
superio/ite/it8772f/chip.h: Use 'bool' when appropriate
Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/jecht')
| -rw-r--r-- | src/mainboard/google/jecht/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 59cf07162988..1bf8a2aefb2a 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -73,7 +73,7 @@ chip soc/intel/broadwell end chip superio/ite/it8772f # Skip keyboard init - register "skip_keyboard" = "1" + register "skip_keyboard" = "true" # Enable PECI on TMPIN3 register "peci_tmpin" = "3" # Disable use of TMPIN1 @@ -81,7 +81,7 @@ chip soc/intel/broadwell # Enable Thermal Diode on TMPIN2 register "tmpin2_mode" = "1" # Enable FAN2 - register "fan2_enable" = "1" + register "fan2_enable" = "true" # Default FAN2 speed register "fan2_speed" = "0x4d" |