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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2013-08-13 10:50:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 12:17:54 +0100 |
| commit | c59fda321697974d467dc7ae8f7b22b43a1899af (patch) | |
| tree | 97e02e42b418845c7b69dda057324e28470a834e /src/mainboard/google/peppy | |
| parent | 287522749ececda35b52dc9b9e8e704e305ec888 (diff) | |
| download | coreboot-c59fda321697974d467dc7ae8f7b22b43a1899af.tar.gz coreboot-c59fda321697974d467dc7ae8f7b22b43a1899af.tar.bz2 coreboot-c59fda321697974d467dc7ae8f7b22b43a1899af.zip | |
peppy: Set optimal DTLE register values
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
EDGE on Peppy.
Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65717
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/peppy')
| -rw-r--r-- | src/mainboard/google/peppy/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 06ca93c9f443..b19f04bf88ca 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -70,6 +70,10 @@ chip northbridge/intel/haswell register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + register "sio_acpi_mode" = "0" register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V |