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| author | Shelley Chen <shchen@google.com> | 2024-01-12 18:50:11 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2024-01-17 05:19:53 +0000 |
| commit | d1a940c7534d14e62d6647e27b255544b60939ca (patch) | |
| tree | d10f5e7f91d567c35ac4f66f5fb5008ec36c5c84 /src/mainboard/google | |
| parent | ab9c751404467575690d6925af8c3afde83c3e64 (diff) | |
| download | coreboot-d1a940c7534d14e62d6647e27b255544b60939ca.tar.gz coreboot-d1a940c7534d14e62d6647e27b255544b60939ca.tar.bz2 coreboot-d1a940c7534d14e62d6647e27b255544b60939ca.zip | |
mb/google/brox: Move storage devices to overridetree
These are specific to the brox board, so moving devices to the brox
variant.
BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb | 15 | ||||
| -rw-r--r-- | src/mainboard/google/brox/variants/brox/overridetree.cb | 19 |
2 files changed, 19 insertions, 15 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f82447324fd5..5589bbe3565f 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -187,21 +187,6 @@ chip soc/intel/alderlake end device ref heci1 on end device ref sata on end - device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 3 - register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_req = 3, - .clk_src = 3, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end - device ref ish on - chip drivers/intel/ish - register "add_acpi_dma_property" = "true" - device generic 0 on end - end - end - device ref ufs on end device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 4aaaf5fe6055..0086099a41af 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -172,5 +172,24 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS + end end end |