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| author | Furquan Shaikh <furquan@google.com> | 2021-10-25 15:47:39 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-10-26 23:22:00 +0000 |
| commit | d06c09179a277a22ee3c14afe0e8f0c51ea74277 (patch) | |
| tree | 2d528191919efe5761bc101ded20f3da8bf7be5d /src/mainboard/intel/adlrvp | |
| parent | 10796d8c1e446d677c563280f9d7ca1905218041 (diff) | |
| download | coreboot-d06c09179a277a22ee3c14afe0e8f0c51ea74277.tar.gz coreboot-d06c09179a277a22ee3c14afe0e8f0c51ea74277.tar.bz2 coreboot-d06c09179a277a22ee3c14afe0e8f0c51ea74277.zip | |
intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmd
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 28cda245e46b..ef3320f746d7 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,14 +1,20 @@ FLASH 32M { SI_ALL 6M { SI_DESC 4K - SI_ME + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 4032K + } } SI_BIOS 26M { RW_SECTION_A 8M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M + ME_RW_A(CBFS) 4032K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -32,7 +38,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M + ME_RW_B(CBFS) 4032K } # Make WP_RO region align with SPI vendor # memory protected range specification. |