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| author | pchandri <preetham.chandrian@intel.com> | 2015-09-14 14:11:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:15:30 +0100 |
| commit | e57e72681fa218bb747f658576c64111c20363e3 (patch) | |
| tree | 380bf4a6c7488c2c5f3b0818289d7e152c2a7e69 /src/mainboard/intel/kunimitsu/romstage.c | |
| parent | b45dde0b78cbe646e12316408ac67cdc72ed9a9d (diff) | |
| download | coreboot-e57e72681fa218bb747f658576c64111c20363e3.tar.gz coreboot-e57e72681fa218bb747f658576c64111c20363e3.tar.bz2 coreboot-e57e72681fa218bb747f658576c64111c20363e3.zip | |
intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value
This patch strengthens the Rcomp Target CTRL by 10% for
8GB memory part K4E6E304EE-EGCF as with the current values
the MRC training is failing due to more load on CS#
BRANCH=None
BUG=chrome-os-partner:44647
TEST=BUilds and boots on Kunimitsu.
Change-Id: I478002bbebabaac418356d4b5b4755bb56009268
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d
Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304103
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12143
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/romstage.c')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/romstage.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index a0eeafc9a573..cd855d681d17 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> @@ -40,11 +40,21 @@ static void early_config_gpio(void) void mainboard_romstage_entry(struct romstage_params *params) { + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); early_config_gpio(); + params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, + ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); |