diff options
author | Subrata Banik <subrata.banik@intel.com> | 2019-10-30 16:48:19 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:50:03 +0000 |
commit | 2715cdb3f32fcebdd1de6870a665a2b613c07e60 (patch) | |
tree | 5addc7091dfc055927c7edbbb44f36a45114e77c /src/mainboard/intel | |
parent | 1e8f305957c98cb224574e1fa81938c9a692bd48 (diff) | |
download | coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.gz coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.bz2 coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.zip |
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
24 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 2e3fa7ac449b..9dd8879706cb 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -33,6 +33,6 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index c713330f3849..28d743e598f4 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -52,5 +52,5 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl index 3719154bdd01..bea6af79736f 100644 --- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl +++ b/src/mainboard/intel/bayleybay_fsp/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d2388fb1..acc4c7c7c3cc 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -45,6 +45,6 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6ded8e..f83003531813 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -45,6 +45,6 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 8dc11942a0f6..dc1dacc66bc4 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 95ed8d913d38..afc53861bbfb 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 60f4c74241d8..9d1d26198fa7 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 002dfcaeb651..e0e3a3a94bbf 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 911dceeaf34a..75073caed278 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 45968fbfc3aa..d9792ff9d5c4 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -53,5 +53,5 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 759d669f8a0c..d7711be75d8b 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 9bc42cf4de4c..2636df15a60a 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/denverton_ns/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469faaa7d7..6657a6ed6e54 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -60,7 +60,7 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 8a165518b760..059bcd54c322 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -57,7 +57,7 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index af5f99d81530..6dab56ea779b 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -49,7 +49,7 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 48b24b9190a6..6fccf4917c65 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -39,5 +39,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index 310ad04741ac..e5cd0ea1a191 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -49,5 +49,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 48b24b9190a6..6fccf4917c65 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -39,5 +39,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl index 3719154bdd01..bea6af79736f 100644 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index 310ad04741ac..e5cd0ea1a191 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -49,5 +49,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index ac929a6bc43d..86ea299aa950 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 5052ba265c41..e89b88797fab 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -58,7 +58,7 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ - #include <acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 42fd7eab9547..ef3e2319d135 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -53,7 +53,7 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> // Mainboard specific #include "acpi/mainboard.asl" |