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| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-22 17:59:38 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-28 04:26:53 +0000 |
| commit | 43fd0402265c0c1381fc3fcf04610ed9f2781f2f (patch) | |
| tree | d56ea00ec8a9082c26a9f5d0e0dcac349811c7b7 /src/mainboard/intel | |
| parent | fa6d31f9997278714d409512b0f77acbf55b32e2 (diff) | |
| download | coreboot-43fd0402265c0c1381fc3fcf04610ed9f2781f2f.tar.gz coreboot-43fd0402265c0c1381fc3fcf04610ed9f2781f2f.tar.bz2 coreboot-43fd0402265c0c1381fc3fcf04610ed9f2781f2f.zip | |
mb/intel/adlrvp_m: Enable TCSS USB ports device path
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ae248429a9d0..0462a2bb8f92 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -162,7 +162,21 @@ chip soc/intel/alderlake device ref pcie4_1 on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end - device ref tcss_xhci on end + device ref tcss_xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TypeC Port 1"" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""TypeC Port 2"" + device ref tcss_usb3_port2 on end + end + end + end + end device ref tcss_dma0 on end device ref xhci on chip drivers/usb/acpi |