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| author | Deepti Deshatty <deepti.deshatty@intel.com> | 2021-05-12 17:45:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 10:09:04 +0000 |
| commit | 8e7facf3437d633af747f6163cd66525ea14860e (patch) | |
| tree | c361c457b54cabb04f430bf6def72fad6e9aa7e0 /src/mainboard/intel | |
| parent | d5433afb28ad6e9c3435310032ed8c7415d1875f (diff) | |
| download | coreboot-8e7facf3437d633af747f6163cd66525ea14860e.tar.gz coreboot-8e7facf3437d633af747f6163cd66525ea14860e.tar.bz2 coreboot-8e7facf3437d633af747f6163cd66525ea14860e.zip | |
soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.
TEST=Verified superspeed pendrive detection on coldboot.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index beaf8fd1ec6d..55d250539c97 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -14,8 +14,7 @@ chip soc/intel/alderlake # TCSS register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x09020005" - register "IomTypeCPortPadCfg[1]" = "0x09020006" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" # Enable heci communication register "HeciEnabled" = "1" |