sb/intel: Use `bool` for PCIe coalescing option

Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.

Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 12 insertions, 12 deletions

diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 86205f8f8481..6c2dabeabb79 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi6_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x3b"
 
diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb
index 3c1fc9e07383..14d849def9c4 100644
--- a/src/mainboard/lenovo/s230u/devicetree.cb
+++ b/src/mainboard/lenovo/s230u/devicetree.cb
@@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi7_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x5"
 			register "superspeed_capable_ports" = "0x0000000f"
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 457ccbee1bee..c934f5fe068a 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# device specific SPI configuration
 			register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 32736a83f2c8..1d6adaf3a8cc 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# device specific SPI configuration
 			register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 112dfe71e79d..141faa930c7b 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -35,7 +35,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi1_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x17"
 			register "superspeed_capable_ports" = "0x0000000f"
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 75a65f900002..942f0299896d 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "docking_supported" = "1"
 
 			register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index a1e24d525b6a..9c75231efc41 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "gen4_dec" = "0x0c06a1"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index ffa0b93e530c..5cfa2075644c 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -52,7 +52,7 @@ chip northbridge/intel/sandybridge
 			register "gen4_dec" = "0x0c06a1"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
 
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index abe40b19dc44..ee8a2e083a12 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x00000c03"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 30260b0c13ad..cbf1141aec8e 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index b239d64daec4..923c88bc31e8 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 1f813116851e..30a79162d4b1 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"