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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-16 11:22:04 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-08-21 21:21:08 +0000 |
| commit | c25f00acfa381703d9ccff4fa5db3b10162b7ab2 (patch) | |
| tree | fd5e8aa0e13f9cbd3038ffdd56c652a33e5f739c /src/mainboard/msi/ms7e06/bootblock.c | |
| parent | c651a27b533289211b3f4a65daa604aac1fc2fb2 (diff) | |
| download | coreboot-c25f00acfa381703d9ccff4fa5db3b10162b7ab2.tar.gz coreboot-c25f00acfa381703d9ccff4fa5db3b10162b7ab2.tar.bz2 coreboot-c25f00acfa381703d9ccff4fa5db3b10162b7ab2.zip | |
mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)
TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core
i5-13600K using UEFI Payload.
Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/msi/ms7e06/bootblock.c')
| -rw-r--r-- | src/mainboard/msi/ms7e06/bootblock.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c new file mode 100644 index 000000000000..110d6828a611 --- /dev/null +++ b/src/mainboard/msi/ms7e06/bootblock.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) + +void bootblock_mainboard_early_init(void) +{ + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ + pnp_write_config(SERIAL_DEV, 0x15, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1a, 0x02); + pnp_write_config(SERIAL_DEV, 0x1b, 0x02); + pnp_write_config(SERIAL_DEV, 0x1d, 0x00); + pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); + pnp_write_config(SERIAL_DEV, 0x22, 0xbd); + pnp_write_config(SERIAL_DEV, 0x23, 0xdf); + pnp_write_config(SERIAL_DEV, 0x24, 0x39); + pnp_write_config(SERIAL_DEV, 0x25, 0xfe); + pnp_write_config(SERIAL_DEV, 0x26, 0x40); + pnp_write_config(SERIAL_DEV, 0x27, 0x77); + pnp_write_config(SERIAL_DEV, 0x28, 0x00); + pnp_write_config(SERIAL_DEV, 0x29, 0xfb); + pnp_write_config(SERIAL_DEV, 0x2a, 0x80); + pnp_write_config(SERIAL_DEV, 0x2b, 0x20); + pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); + pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + + nuvoton_pnp_exit_conf_state(POWER_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} |