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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-08 17:12:13 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-08 15:31:44 +0000 |
| commit | 02db6b40499a1c970f32074bcff5b7b65bec4fa3 (patch) | |
| tree | 4c6515666eba656aea1109858e8ec7daf0fffc83 /src/mainboard/msi | |
| parent | bb1a0e82d7923d93ad296f95f33269a56a01fb1f (diff) | |
| download | coreboot-02db6b40499a1c970f32074bcff5b7b65bec4fa3.tar.gz coreboot-02db6b40499a1c970f32074bcff5b7b65bec4fa3.tar.bz2 coreboot-02db6b40499a1c970f32074bcff5b7b65bec4fa3.zip | |
mb/msi/ms7d25: Add correct memory init configuration
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.
TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/mainboard/msi')
| -rw-r--r-- | src/mainboard/msi/ms7d25/romstage_fsp_params.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 210af0576c33..60f2371dfb00 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -9,18 +9,13 @@ static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistor FIXME */ - .resistor = 100, - - /* Baseboard Rcomp target values FIXME */ - .targets = { 50, 20, 25, 25, 25 }, - }, + /* According to DOC #573387 rcomp values no longer have to be provided */ + /* DDR DIMM configuration does not need to set DQ/DQS maps */ .UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */ .ddr_config = { - .dq_pins_interleaved = false, /* FIXME */ + .dq_pins_interleaved = true, }, }; |