mb/*/*: Drop FSP_BAYTRAIL support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

23 files changed, 0 insertions, 1587 deletions

diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig
deleted file mode 100644
index ddacbe747cd9..000000000000
--- a/src/mainboard/opencellular/rotundu/Kconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-## Copyright (C) 2017-present Facebook, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
-	def_bool n
-	select SOC_INTEL_FSP_BAYTRAIL
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select ENABLE_BUILTIN_COM1
-	select ENABLE_FSP_FAST_BOOT
-	select USE_BLOBS
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-	select MAINBOARD_HAS_LPC_TPM
-	select MAINBOARD_HAS_TPM1
-
-if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
-
-config VBOOT
-	select MRC_CACHE_FMAP
-	select VBOOT_VBNV_CMOS
-	select VBOOT_NO_BOARD_SUPPORT
-	select GBB_FLAG_DISABLE_LID_SHUTDOWN
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_FWMP
-
-config GBB_HWID
-	string
-	depends on VBOOT
-	default "ROTUNDU" if BOARD_OPENCELLULAR_ROTUNDU
-	default "SUPABRCKV1" if BOARD_OPENCELLULAR_SUPABRCKV1
-
-config VARIANT_DIR
-	string
-	default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU
-	default "supabrckv1" if BOARD_OPENCELLULAR_SUPABRCKV1
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Rotundu" if BOARD_OPENCELLULAR_ROTUNDU
-	default "Supabrck v1" if BOARD_OPENCELLULAR_SUPABRCKV1
-
-config DEVICETREE
-	string
-	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config MAINBOARD_DIR
-	string
-	default "opencellular/rotundu"
-
-config MAINBOARD_VENDOR
-	string
-	default "OpenCellular"
-
-config MAX_CPUS
-	int
-	default 16
-
-config FSP_LOC
-	hex
-	default 0xfffb0000
-
-config FMDFILE
-	string
-	depends on VBOOT
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" if BOARD_ROMSIZE_KB_16384
-
-config CBFS_SIZE
-	hex
-	default 0x00140000 if BOARD_ROMSIZE_KB_8192
-	default 0x003effc0 if BOARD_ROMSIZE_KB_16384
-
-config VIRTUAL_ROM_SIZE
-	hex
-	depends on ENABLE_FSP_FAST_BOOT
-	default 0x800000
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config VGA_BIOS
-	bool
-	default y if FSP_PACKAGE_DEFAULT
-
-config VGA_BIOS_ID
-	string
-	default "8086,0f31"
-
-endif # BOARD_OPENCELLULAR_ROTUNDU
diff --git a/src/mainboard/opencellular/rotundu/Kconfig.name b/src/mainboard/opencellular/rotundu/Kconfig.name
deleted file mode 100644
index 1346b94b04c4..000000000000
--- a/src/mainboard/opencellular/rotundu/Kconfig.name
+++ /dev/null
@@ -1,7 +0,0 @@
-config BOARD_OPENCELLULAR_ROTUNDU
-	bool "OpenCellular Rotundu (GBCv1)"
-	select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
-
-config BOARD_OPENCELLULAR_SUPABRCKV1
-	bool "OpenCellular Supabrck V1 (BRCK)"
-	select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
diff --git a/src/mainboard/opencellular/rotundu/Makefile.inc b/src/mainboard/opencellular/rotundu/Makefile.inc
deleted file mode 100644
index 2aee2286f59e..000000000000
--- a/src/mainboard/opencellular/rotundu/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += variants/$(VARIANT_DIR)/gpio.c
-ramstage-y += irqroute.c
-
-subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/opencellular/rotundu/acpi/ec.asl b/src/mainboard/opencellular/rotundu/acpi/ec.asl
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/src/mainboard/opencellular/rotundu/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/opencellular/rotundu/acpi/mainboard.asl b/src/mainboard/opencellular/rotundu/acpi/mainboard.asl
deleted file mode 100644
index b032ee189d10..000000000000
--- a/src/mainboard/opencellular/rotundu/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/opencellular/rotundu/acpi/superio.asl b/src/mainboard/opencellular/rotundu/acpi/superio.asl
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/src/mainboard/opencellular/rotundu/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/opencellular/rotundu/acpi_tables.c b/src/mainboard/opencellular/rotundu/acpi_tables.c
deleted file mode 100644
index 7f6abd96856a..000000000000
--- a/src/mainboard/opencellular/rotundu/acpi_tables.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include <soc/iomap.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	acpi_init_gnvs(gnvs);
-
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-	gnvs->s5u1 = 0;
-
-	/* TPM Present */
-	gnvs->tpmp = 1;
-
-	/* Enable DPTF */
-	gnvs->dpte = 0;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	current = acpi_madt_irq_overrides(current);
-
-	return current;
-}
diff --git a/src/mainboard/opencellular/rotundu/board_info.txt b/src/mainboard/opencellular/rotundu/board_info.txt
deleted file mode 100644
index 115b8be27373..000000000000
--- a/src/mainboard/opencellular/rotundu/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: Rotundu
-Category: sbc
-ROM protocol: SPI
-ROM socketed: n
diff --git a/src/mainboard/opencellular/rotundu/chromeos.fmd b/src/mainboard/opencellular/rotundu/chromeos.fmd
deleted file mode 100644
index 7be08dc27b28..000000000000
--- a/src/mainboard/opencellular/rotundu/chromeos.fmd
+++ /dev/null
@@ -1,37 +0,0 @@
-FLASH@0xff800000 0x800000 {
-	SI_ALL@0x0 0x300000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x2ff000
-	}
-	SI_BIOS@0x300000 0x500000 {
-		RW_SECTION_A@0x0 0xf0000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0xc0000
-			RW_FWID_A@0xeffc0 0x40
-		}
-		RW_SECTION_B@0xf0000 0xf0000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0xc0000
-			RW_FWID_B@0xeffc0 0x40
-		}
-		RW_MRC_CACHE@0x1e0000 0x10000
-		RW_ELOG(PRESERVE)@0x1f0000 0x4000
-		RW_SHARED@0x1f4000 0x4000 {
-			SHARED_DATA@0x0 0x2000
-			VBLOCK_DEV@0x2000 0x2000
-		}
-		RW_VPD(PRESERVE)@0x1f8000 0x2000
-		RW_UNUSED@0x1fa000 0x106000
-		WP_RO@0x300000 0x200000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_UNUSED@0x4000 0xc000
-			RO_SECTION@0x10000 0x1f0000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x100000
-			}
-		}
-	}
-}
diff --git a/src/mainboard/opencellular/rotundu/cmos.default b/src/mainboard/opencellular/rotundu/cmos.default
deleted file mode 100644
index 6c96947e2ac3..000000000000
--- a/src/mainboard/opencellular/rotundu/cmos.default
+++ /dev/null
@@ -1 +0,0 @@
-debug_level=Error
diff --git a/src/mainboard/opencellular/rotundu/cmos.layout b/src/mainboard/opencellular/rotundu/cmos.layout
deleted file mode 100644
index 9ef1102c1742..000000000000
--- a/src/mainboard/opencellular/rotundu/cmos.layout
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2017-present Facebook, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-411          2       e       8        use_xhci_over_ehci
-#413          3       r       0        unused
-
-# MRC Scrambler Seed values
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-8     0     EHCI
-8     1     XHCI
-8     2     Default
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/opencellular/rotundu/dsdt.asl b/src/mainboard/opencellular/rotundu/dsdt.asl
deleted file mode 100644
index bea6af79736f..000000000000
--- a/src/mainboard/opencellular/rotundu/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define INCLUDE_LPE  1
-#define INCLUDE_SCC  1
-#define INCLUDE_EHCI 1
-#define INCLUDE_XHCI 1
-#define INCLUDE_LPSS 1
-
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include <soc/intel/fsp_baytrail/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
-
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
-		}
-	}
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/opencellular/rotundu/fadt.c b/src/mainboard/opencellular/rotundu/fadt.c
deleted file mode 100644
index 4194bfc32493..000000000000
--- a/src/mainboard/opencellular/rotundu/fadt.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	acpi_fill_in_fadt(fadt, facs, dsdt);
-
-	/* Platform specific customizations go here */
-
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/opencellular/rotundu/irqroute.c b/src/mainboard/opencellular/rotundu/irqroute.c
deleted file mode 100644
index db8c512a4398..000000000000
--- a/src/mainboard/opencellular/rotundu/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/opencellular/rotundu/irqroute.h b/src/mainboard/opencellular/rotundu/irqroute.h
deleted file mode 100644
index 9feaa0ed9ec6..000000000000
--- a/src/mainboard/opencellular/rotundu/irqroute.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
-
-/*
- *IR02h GFX      INT(A)     - PIRQ A
- *IR10h EMMC     INT(ABCD)  - PIRQ DEFG
- *IR11h SDIO     INT(A)     - PIRQ B
- *IR12h SD       INT(A)     - PIRQ C
- *IR13h SATA     INT(A)     - PIRQ D
- *IR14h XHCI     INT(A)     - PIRQ E
- *IR15h LP Audio INT(A)     - PIRQ F
- *IR17h MMC      INT(A)     - PIRQ F
- *IR18h SIO      INT(ABCD)  - PIRQ BADC
- *IR1Ah TXE      INT(A)     - PIRQ F
- *IR1Bh HD Audio INT(A)     - PIRQ G
- *IR1Ch PCIe     INT(ABCD)  - PIRQ EFGH
- *IR1Dh EHCI     INT(A)     - PIRQ D
- *IR1Eh SIO      INT(ABCD)  - PIRQ BDEF
- *IR1Fh LPC      INT(ABCD)  - PIRQ HGBC
- */
-
-/* PCIe bridge routing */
-#define BRIDGE1_DEV PCIE_DEV
-
-/* PCI bridge IRQs need to be updated in both tables and need to match */
-#define PCIE_BRIDGE_IRQ_ROUTES \
-	PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV,    E, F, G, H)
-
-/* Devices set as A, A, A, A evaluate as 0, and don't get set */
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(GFX_DEV,     A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,    D, E, F, G), \
-	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,    B, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SD_DEV,      C, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA_DEV,    D, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,    E, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(LPE_DEV,     F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,   F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,    B, A, D, C), \
-	PCI_DEV_PIRQ_ROUTE(TXE_DEV,     F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(HDA_DEV,     G, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,    D, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,    B, D, E, F), \
-	PCI_DEV_PIRQ_ROUTE(PCU_DEV,     H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A,  4), \
-	PIRQ_PIC(B,  5), \
-	PIRQ_PIC(C,  7), \
-	PIRQ_PIC(D, 10), \
-	PIRQ_PIC(E, 11), \
-	PIRQ_PIC(F, 12), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/opencellular/rotundu/mainboard.c b/src/mainboard/opencellular/rotundu/mainboard.c
deleted file mode 100644
index 53c98002e90a..000000000000
--- a/src/mainboard/opencellular/rotundu/mainboard.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-}
-
-/*
- * mainboard_final is executed as one of the last items before loading the
- * payload.
- *
- * This is the latest point to add customization.
- */
-static void mainboard_final(void *chip_info)
-{
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-	.final = mainboard_final,
-};
diff --git a/src/mainboard/opencellular/rotundu/romstage.c b/src/mainboard/opencellular/rotundu/romstage.c
deleted file mode 100644
index b5c3bc8fc384..000000000000
--- a/src/mainboard/opencellular/rotundu/romstage.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Intel Corporation
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <soc/gpio.h>
-#include <soc/romstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <soc/intel/fsp_baytrail/chip.h>
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param fd_mask
- * @param fd2_mask
- */
-void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
-{
-
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-
-}
-
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	printk(BIOS_NOTICE, "This is the OpenCellular Rotundu GBC board.\n");
-}
diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb
deleted file mode 100644
index 7eeac7ad841b..000000000000
--- a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-## Copyright (C) 2017-present Facebook, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/fsp_baytrail
-
-	#### ACPI Register Settings ####
-	register "fadt_pm_profile" = "PM_UNSPECIFIED"
-	register "fadt_boot_arch"  = "ACPI_FADT_LEGACY_FREE"
-
-	#### FSP register settings ####
-	register "PcdSataMode"             = "SATA_MODE_AHCI"
-	register "PcdMrcInitSPDAddr1"      = "0xa0"
-	register "PcdMrcInitSPDAddr2"      = "0xa2"
-	register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
-	register "PcdeMMCBootMode"         = "EMMC_DISABLED"
-	register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
-	register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"
-	register "PcdGttSize"              = "GTT_SIZE_DEFAULT"
-	register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
-	register "AzaliaAutoEnable"     = "AZALIA_FOLLOWS_DEVICETREE"
-	register "LpeAcpiModeEnable"    = "LPE_ACPI_MODE_DISABLED"
-	register "EnableMemoryDown"     = "MEMORY_DOWN_DISABLE"
-	register "DIMM0Enable"          = "DIMM0_ENABLE"
-	register "DIMM1Enable"          = "DIMM1_DISABLE"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end	# 8086 0F00 - SoC router
-		device pci 02.0 on end	# 8086 0F31 - GFX
-		device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
-
-		device pci 10.0 off end	# 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port (SD2 pins)
-		device pci 12.0 off end	# 8086 0F16 - SD Port (SD3 pins)
-		device pci 13.0 on end	# 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
-		device pci 14.0 on end	# 8086 0F35 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 off end	# 8086 0F28 - LP Engine Audio
-		device pci 16.0 off end # 8086 0F37 - OTG controller
-		device pci 17.0 off end	# 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
-		device pci 18.0 on end	# 8086 0F40 - SIO - DMA
-		device pci 18.1 on end	# 8086 0F41 -   I2C Port 1
-		device pci 18.2 off end	# 8086 0F42 -   I2C Port 2
-		device pci 18.3 on end	# 8086 0F43 -   I2C Port 3
-		device pci 18.4 off end	# 8086 0F44 -   I2C Port 4
-		device pci 18.5 off end	# 8086 0F45 -   I2C Port 5
-		device pci 18.6 off end	# 8086 0F46 -   I2C Port 6
-		device pci 18.7 off end	# 8086 0F47 -   I2C Port 7
-		device pci 1a.0 on end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 off end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
-		device pci 1c.1 on end	# 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
-		device pci 1c.2 on end	# 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
-		device pci 1c.3 off end	# 8086 0F4E - PCIe Root Port 4 (NC)
-		device pci 1d.0 off end	# 8086 0F34 - USB EHCI - Only 1 USB controller at a time
-		device pci 1e.0 on end	# 8086 0F06 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 0F0A -   HSUART 1
-		device pci 1e.4 off end	# 8086 0F0C -   HSUART 2
-		device pci 1e.5 off end	# 8086 0F0E -   SPI
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end	# 8086 0F1C - LPC bridge
-		device pci 1f.3 on end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
deleted file mode 100644
index 78d1ad6ae21a..000000000000
--- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <soc/gpio.h>
-#include "../../irqroute.h"
-
-/* NCORE GPIOs */
-static const struct soc_gpio_map gpncore_gpio_map[] = {
-
-	GPIO_FUNC2, /* GPIO 0 */
-	GPIO_FUNC2, /* GPIO 1 */
-	GPIO_FUNC2, /* GPIO 2 */
-	GPIO_FUNC2, /* GPIO 3 */
-	GPIO_FUNC2, /* GPIO 4 */
-	GPIO_FUNC2, /* GPIO 5 */
-	GPIO_FUNC2, /* GPIO 6 */
-	GPIO_FUNC2, /* GPIO 7 */
-	GPIO_FUNC2, /* GPIO 8 */
-	GPIO_FUNC2, /* GPIO 9 */
-	GPIO_FUNC2, /* GPIO 10 */
-	GPIO_FUNC2, /* GPIO 11 */
-	GPIO_FUNC2, /* GPIO 12 */
-	GPIO_FUNC2, /* GPIO 13 */
-	GPIO_FUNC2, /* GPIO 14 */
-	GPIO_FUNC2, /* GPIO 15 */
-	GPIO_FUNC2, /* GPIO 16 */
-	GPIO_FUNC2, /* GPIO 17 */
-	GPIO_FUNC2, /* GPIO 18 */
-	GPIO_FUNC2, /* GPIO 19 */
-	GPIO_FUNC2, /* GPIO 20 */
-	GPIO_FUNC2, /* GPIO 21 */
-	GPIO_FUNC2, /* GPIO 22 */
-	GPIO_FUNC2, /* GPIO 23 */
-	GPIO_FUNC2, /* GPIO 24 */
-	GPIO_FUNC2, /* GPIO 25 */
-	GPIO_FUNC2, /* GPIO 26 */
-	GPIO_END};
-
-/* SCORE GPIOs (GPIO_S0_SC_XX) */
-static const struct soc_gpio_map gpscore_gpio_map[] = {
-	GPIO_NC,
-	/* GPIO_S0_SC[000] SATA_GP[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[002] SATA_LED# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
-	GPIO_FUNC2,
-	/* GPIO_S0_SC[007] RESERVED SD3_WP */
-	GPIO_NC,
-	/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
-	GPIO_NC,
-	/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
-	GPIO_NC,
-	/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
-	GPIO_NC,
-	/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
-	GPIO_NC,
-	/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
-	GPIO_NC,
-	/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
-	GPIO_NC,
-	/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
-	GPIO_NC,
-	/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
-	GPIO_NC,
-	/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
-	GPIO_NC,
-	/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
-	GPIO_NC,
-	/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
-	GPIO_NC,
-	/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
-	GPIO_NC,
-	/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
-	GPIO_NC,
-	/* GPIO_S0_SC[027] SD2_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[028] SD2_D[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[029] SD2_D[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[030] SD2_D[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[031] SD2_D[3]_CD# */
-	GPIO_NC,
-	/* GPIO_S0_SC[032] SD2_CMD */
-	GPIO_NC,
-	/* GPIO_S0_SC[033] SD3_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[034] SD3_D[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[035] SD3_D[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[036] SD3_D[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[037] SD3_D[3] */
-	GPIO_NC,
-	/* GPIO_S0_SC[038] SD3_CD# */
-	GPIO_NC,
-	/* GPIO_S0_SC[039] SD3_CMD */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[040] SD3_1P8EN */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[041] SD3_PWREN# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[051] PCU_SMB_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[052] PCU_SMB_CLK */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
-	GPIO_NC,
-	/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[055] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[056] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[057] PCU_UART_TXD */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[058] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[059] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[060] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[061] PCU_UART_RXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
-	GPIO_NC,
-	/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
-	GPIO_NC,
-	/* GPIO_S0_SC[066] SIO_SPI_CS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[067] SIO_SPI_MISO */
-	GPIO_NC,
-	/* GPIO_S0_SC[068] SIO_SPI_MOSI */
-	GPIO_NC,
-	/* GPIO_S0_SC[069] SIO_SPI_CLK */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
-	GPIO_NC,
-	/* GPIO_S0_SC[072] SIO_UART1_RTS# */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[073] SIO_UART1_CTS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[074] SIO_UART2_RXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[075] SIO_UART2_TXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[076] SIO_UART2_RTS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[077] SIO_UART2_CTS# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[078] SIO_I2C0_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[079] SIO_I2C0_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[080] SIO_I2C1_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[082] SIO_I2C2_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[083] SIO_I2C2_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[084] SIO_I2C3_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[085] SIO_I2C3_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[086] SIO_I2C4_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[087] SIO_I2C4_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[088] SIO_I2C5_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[089] SIO_I2C5_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
-	GPIO_NC,
-	/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
-	GPIO_NC,
-	/* RESERVED  GPIO_S0_SC[092] */
-	GPIO_NC,
-	/* RESERVED  GPIO_S0_SC[093] */
-	GPIO_NC,
-	/* GPIO_S0_SC[094] SIO_PWM[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[095] SIO_PWM[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
-	GPIO_NC,
-	/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
-	GPIO_NC,
-	/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
-	GPIO_END};
-
-/* SSUS GPIOs (GPIO_S5) */
-static const struct soc_gpio_map gpssus_gpio_map[] = {
-	GPIO_DEFAULT,
-	/* GPIO_S5[00] RESERVED- */
-	GPIO_NC,
-	/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
-	GPIO_DEFAULT,
-	/* PMC_SUSPWRDNACK GPIO_S5[11]*/
-	GPIO_NC,
-	/* PMC_SUSCLK[0] GPIO_S5[12]*/
-	GPIO_NC,
-	/* RESERVED GPIO_S5[13]*/
-	GPIO_FUNC2,
-	/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
-	GPIO_FUNC0,
-	/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
-	GPIO_FUNC0,
-	/* PMC_PWRBTN# GPIO_S5[16]*/
-	GPIO_FUNC1,
-	/* RESERVED GPIO_S5[17]*/
-	GPIO_FUNC0,
-	/* PMC_SUS_STAT# GPIO_S5[18]*/
-	GPIO_FUNC0,
-	/* USB_OC[0]# GPIO_S5[19]*/
-	GPIO_FUNC0,
-	/* USB_OC[1]# GPIO_S5[20]*/
-	GPIO_NC,
-	/* PCU_SPI_CS[1]# GPIO_S5[21]*/
-	GPIO_NC,
-	/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
-	GPIO_END};
-
-static struct soc_gpio_config gpio_config = {
-	.ncore = gpncore_gpio_map,
-	.score = gpscore_gpio_map,
-	.ssus = gpssus_gpio_map,
-	.core_dirq = NULL,
-	.sus_dirq = NULL,
-};
-
-struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
deleted file mode 100644
index c0bd2f0fe23f..000000000000
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-## Copyright (C) 2017-present Facebook, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/fsp_baytrail
-
-	#### ACPI Register Settings ####
-	register "fadt_pm_profile" = "PM_UNSPECIFIED"
-	register "fadt_boot_arch"  = "ACPI_FADT_LEGACY_FREE"
-
-	#### FSP register settings ####
-	register "PcdSataMode"             = "SATA_MODE_AHCI"
-	register "PcdMrcInitSPDAddr1"      = "0xa0"
-	register "PcdMrcInitSPDAddr2"      = "0xa2"
-	register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
-	register "PcdeMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
-	register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
-	register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"
-	register "PcdGttSize"              = "GTT_SIZE_DEFAULT"
-	register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
-	register "AzaliaAutoEnable"     = "AZALIA_FOLLOWS_DEVICETREE"
-	register "LpeAcpiModeEnable"    = "LPE_ACPI_MODE_DISABLED"
-	register "EnableMemoryDown"     = "MEMORY_DOWN_DISABLE"
-	register "DIMM0Enable"          = "DIMM0_ENABLE"
-	register "DIMM1Enable"          = "DIMM1_DISABLE"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end	# 8086 0F00 - SoC router
-		device pci 02.0 on end	# 8086 0F31 - GFX
-		device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
-
-		device pci 10.0 off end	# 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port (SD2 pins)
-		device pci 12.0 off end	# 8086 0F16 - SD Port (SD3 pins)
-		device pci 13.0 on end	# 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
-		device pci 14.0 on end	# 8086 0F35 - USB XHCI - Only 1 USB controller at a time
-		device pci 15.0 off end	# 8086 0F28 - LP Engine Audio
-		device pci 16.0 off end # 8086 0F37 - OTG controller
-		device pci 17.0 on end	# 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
-		device pci 18.0 on end	# 8086 0F40 - SIO - DMA
-		device pci 18.1 on end	# 8086 0F41 -   I2C Port 1
-		device pci 18.2 off end	# 8086 0F42 -   I2C Port 2
-		device pci 18.3 on end	# 8086 0F43 -   I2C Port 3
-		device pci 18.4 off end	# 8086 0F44 -   I2C Port 4
-		device pci 18.5 off end	# 8086 0F45 -   I2C Port 5
-		device pci 18.6 off end	# 8086 0F46 -   I2C Port 6
-		device pci 18.7 off end	# 8086 0F47 -   I2C Port 7
-		device pci 1a.0 on end	# 8086 0F18 - Trusted Execution Engine
-		device pci 1b.0 off end	# 8086 0F04 - HD Audio
-		device pci 1c.0 on end	# 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
-		device pci 1c.1 on end	# 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
-		device pci 1c.2 on end	# 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
-		device pci 1c.3 off end	# 8086 0F4E - PCIe Root Port 4 (NC)
-		device pci 1d.0 off end	# 8086 0F34 - USB EHCI - Only 1 USB controller at a time
-		device pci 1e.0 on end	# 8086 0F06 - SIO - DMA
-		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
-		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
-		device pci 1e.3 on end	# 8086 0F0A -   HSUART 1
-		device pci 1e.4 off end	# 8086 0F0C -   HSUART 2
-		device pci 1e.5 off end	# 8086 0F0E -   SPI
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end	# 8086 0F1C - LPC bridge
-		device pci 1f.3 on end	# 8086 0F12 - SMBus 0
-	end
-end
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
deleted file mode 100644
index c9d54268f70e..000000000000
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2017-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <soc/gpio.h>
-#include "../../irqroute.h"
-
-#define GPIO_FUNC3_PULL_UP_20K          GPIO_FUNC(3, PULL_UP, 20K)
-#define GPIO_FUNC3_PULL_DOWN_20K        GPIO_FUNC(3, PULL_DOWN, 20K)
-
-/* NCORE GPIOs */
-static const struct soc_gpio_map gpncore_gpio_map[] = {
-
-	GPIO_FUNC2, /* GPIO 0 */
-	GPIO_FUNC2, /* GPIO 1 */
-	GPIO_FUNC2, /* GPIO 2 */
-	GPIO_FUNC2, /* GPIO 3 */
-	GPIO_FUNC2, /* GPIO 4 */
-	GPIO_FUNC2, /* GPIO 5 */
-	GPIO_FUNC2, /* GPIO 6 */
-	GPIO_FUNC2, /* GPIO 7 */
-	GPIO_FUNC2, /* GPIO 8 */
-	GPIO_FUNC2, /* GPIO 9 */
-	GPIO_FUNC2, /* GPIO 10 */
-	GPIO_FUNC2, /* GPIO 11 */
-	GPIO_FUNC2, /* GPIO 12 */
-	GPIO_FUNC2, /* GPIO 13 */
-	GPIO_FUNC2, /* GPIO 14 */
-	GPIO_FUNC2, /* GPIO 15 */
-	GPIO_FUNC2, /* GPIO 16 */
-	GPIO_FUNC2, /* GPIO 17 */
-	GPIO_FUNC2, /* GPIO 18 */
-	GPIO_FUNC2, /* GPIO 19 */
-	GPIO_FUNC2, /* GPIO 20 */
-	GPIO_FUNC2, /* GPIO 21 */
-	GPIO_FUNC2, /* GPIO 22 */
-	GPIO_FUNC2, /* GPIO 23 */
-	GPIO_FUNC2, /* GPIO 24 */
-	GPIO_FUNC2, /* GPIO 25 */
-	GPIO_FUNC2, /* GPIO 26 */
-	GPIO_END};
-
-/* SCORE GPIOs (GPIO_S0_SC_XX) */
-static const struct soc_gpio_map gpscore_gpio_map[] = {
-	GPIO_NC,
-	/* GPIO_S0_SC[000] SATA_GP[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[002] SATA_LED# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
-	GPIO_FUNC2,
-	/* GPIO_S0_SC[007] RESERVED SD3_WP */
-	GPIO_NC,
-	/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
-	GPIO_NC,
-	/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
-	GPIO_NC,
-	/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
-	GPIO_NC,
-	/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
-	GPIO_NC,
-	/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
-	GPIO_NC,
-	/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
-	GPIO_FUNC3_PULL_DOWN_20K,
-	/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
-	GPIO_FUNC3_PULL_UP_20K,
-	/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
-	GPIO_FUNC3_PULL_DOWN_20K,
-	/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
-	GPIO_NC,
-	/* GPIO_S0_SC[027] SD2_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[028] SD2_D[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[029] SD2_D[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[030] SD2_D[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[031] SD2_D[3]_CD# */
-	GPIO_NC,
-	/* GPIO_S0_SC[032] SD2_CMD */
-	GPIO_NC,
-	/* GPIO_S0_SC[033] SD3_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[034] SD3_D[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[035] SD3_D[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[036] SD3_D[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[037] SD3_D[3] */
-	GPIO_NC,
-	/* GPIO_S0_SC[038] SD3_CD# */
-	GPIO_NC,
-	/* GPIO_S0_SC[039] SD3_CMD */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[040] SD3_1P8EN */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[041] SD3_PWREN# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[051] PCU_SMB_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[052] PCU_SMB_CLK */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
-	GPIO_NC,
-	/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[055] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[056] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[057] PCU_UART_TXD */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[058] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[059] RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[060] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[061] PCU_UART_RXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
-	GPIO_NC,
-	/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
-	GPIO_NC,
-	/* GPIO_S0_SC[066] SIO_SPI_CS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[067] SIO_SPI_MISO */
-	GPIO_NC,
-	/* GPIO_S0_SC[068] SIO_SPI_MOSI */
-	GPIO_NC,
-	/* GPIO_S0_SC[069] SIO_SPI_CLK */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
-	GPIO_NC,
-	/* GPIO_S0_SC[072] SIO_UART1_RTS# */
-	GPIO_DEFAULT,
-	/* GPIO_S0_SC[073] SIO_UART1_CTS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[074] SIO_UART2_RXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[075] SIO_UART2_TXD */
-	GPIO_NC,
-	/* GPIO_S0_SC[076] SIO_UART2_RTS# */
-	GPIO_NC,
-	/* GPIO_S0_SC[077] SIO_UART2_CTS# */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[078] SIO_I2C0_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[079] SIO_I2C0_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[080] SIO_I2C1_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[082] SIO_I2C2_DATA */
-	GPIO_FUNC1,
-	/* GPIO_S0_SC[083] SIO_I2C2_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[084] SIO_I2C3_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[085] SIO_I2C3_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[086] SIO_I2C4_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[087] SIO_I2C4_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[088] SIO_I2C5_DATA */
-	GPIO_NC,
-	/* GPIO_S0_SC[089] SIO_I2C5_CLK */
-	GPIO_NC,
-	/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
-	GPIO_NC,
-	/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
-	GPIO_NC,
-	/* RESERVED  GPIO_S0_SC[092] */
-	GPIO_NC,
-	/* RESERVED  GPIO_S0_SC[093] */
-	GPIO_NC,
-	/* GPIO_S0_SC[094] SIO_PWM[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[095] SIO_PWM[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
-	GPIO_NC,
-	/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
-	GPIO_NC,
-	/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
-	GPIO_NC,
-	/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
-	GPIO_NC,
-	/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
-	GPIO_NC,
-	/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
-	GPIO_END};
-
-/* SSUS GPIOs (GPIO_S5) */
-static const struct soc_gpio_map gpssus_gpio_map[] = {
-	GPIO_DEFAULT,
-	/* GPIO_S5[00] RESERVED- */
-	GPIO_NC,
-	/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
-	GPIO_DEFAULT,
-	/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
-	GPIO_DEFAULT,
-	/* PMC_SUSPWRDNACK GPIO_S5[11]*/
-	GPIO_NC,
-	/* PMC_SUSCLK[0] GPIO_S5[12]*/
-	GPIO_NC,
-	/* RESERVED GPIO_S5[13]*/
-	GPIO_FUNC2,
-	/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
-	GPIO_FUNC0,
-	/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
-	GPIO_FUNC0,
-	/* PMC_PWRBTN# GPIO_S5[16]*/
-	GPIO_FUNC1,
-	/* RESERVED GPIO_S5[17]*/
-	GPIO_FUNC0,
-	/* PMC_SUS_STAT# GPIO_S5[18]*/
-	GPIO_FUNC0,
-	/* USB_OC[0]# GPIO_S5[19]*/
-	GPIO_FUNC0,
-	/* USB_OC[1]# GPIO_S5[20]*/
-	GPIO_NC,
-	/* PCU_SPI_CS[1]# GPIO_S5[21]*/
-	GPIO_NC,
-	/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_DEFAULT,
-	/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_NC,
-	/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
-	GPIO_FUNC1,
-	/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
-	GPIO_NC,
-	/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
-	GPIO_END};
-
-static struct soc_gpio_config gpio_config = {
-	.ncore = gpncore_gpio_map,
-	.score = gpscore_gpio_map,
-	.ssus = gpssus_gpio_map,
-	.core_dirq = NULL,
-	.sus_dirq = NULL,
-};
-
-struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
diff --git a/src/mainboard/opencellular/rotundu/vboot-16M.fmd b/src/mainboard/opencellular/rotundu/vboot-16M.fmd
deleted file mode 100644
index c1bedbf64b7f..000000000000
--- a/src/mainboard/opencellular/rotundu/vboot-16M.fmd
+++ /dev/null
@@ -1,30 +0,0 @@
-FLASH 16M {
-	SI_ALL@0x0 0x300000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x2ff000
-	}
-	SI_BIOS@0x300000 0xd00000 {
-		RW_SECTION_B@0x0 0x400000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x3effc0
-			RW_FWID_B@0x3fffc0 0x40
-		}
-		RW_SECTION_A@0x400000 0x400000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x3effc0
-			RW_FWID_A@0x3fffc0 0x40
-		}
-		RW_MRC_CACHE@0x800000 0x10000
-		RW_VPD(PRESERVE)@0x810000 0x2000
-		WP_RO@0x812000 0x4ee000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x4ea000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x3fa000
-			}
-		}
-	}
-}
diff --git a/src/mainboard/opencellular/rotundu/vboot-8M.fmd b/src/mainboard/opencellular/rotundu/vboot-8M.fmd
deleted file mode 100644
index 42b8b3151dc0..000000000000
--- a/src/mainboard/opencellular/rotundu/vboot-8M.fmd
+++ /dev/null
@@ -1,30 +0,0 @@
-FLASH 8M {
-	SI_ALL@0x0 0x300000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x2ff000
-	}
-	SI_BIOS@0x300000 0x500000 {
-		RW_SECTION_B@0x0 0x150040 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x140000
-			RW_FWID_B@0x150000 0x40
-		}
-		RW_SECTION_A@0x150040 0x150040 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x140000
-			RW_FWID_A@0x150000 0x40
-		}
-		RW_MRC_CACHE@0x2a0080 0x10000
-		RW_VPD(PRESERVE)@0x2b0080 0x2000
-		WP_RO@0x2b2080 0x24df80 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x249f80 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x159f80
-			}
-		}
-	}
-}