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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-19 12:31:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-21 07:16:01 +0000 |
| commit | f50ea988b09e7201e129848ab64e6e0e69bf56c4 (patch) | |
| tree | e7cf17631d7c3cd41fa3c68a4c578d4ee7e36b8a /src/mainboard/protectli | |
| parent | dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (diff) | |
| download | coreboot-f50ea988b09e7201e129848ab64e6e0e69bf56c4.tar.gz coreboot-f50ea988b09e7201e129848ab64e6e0e69bf56c4.tar.bz2 coreboot-f50ea988b09e7201e129848ab64e6e0e69bf56c4.zip | |
soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/protectli')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/gpio.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h index 4af4b1476a25..7ec5a8a62ba9 100644 --- a/src/mainboard/protectli/vault_kbl/gpio.h +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -11,21 +11,21 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* ISH_GP6 */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -48,7 +48,7 @@ static const struct pad_config gpio_table[] = { /* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), @@ -123,7 +123,7 @@ static const struct pad_config gpio_table[] = { /* DDI4_HPD */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_NC(GPP_E17, NONE), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -163,7 +163,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_NC(GPD0, NONE), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE_N */ PAD_NC(GPD2, NONE), -/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), |