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author | Aaron Durbin <adurbin@chromium.org> | 2016-07-25 21:31:41 -0500 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2016-07-30 01:36:32 +0200 |
commit | b0f81518b5c17466bc95ebdef292e82c4b76bc88 (patch) | |
tree | 7174d0006c9a8450ada5aeb7c6fe6377407e96a6 /src/mainboard/samsung/stumpy/chromeos.c | |
parent | 212820c8d728c59fa3228ce92bc1d549b232e35a (diff) | |
download | coreboot-b0f81518b5c17466bc95ebdef292e82c4b76bc88.tar.gz coreboot-b0f81518b5c17466bc95ebdef292e82c4b76bc88.tar.bz2 coreboot-b0f81518b5c17466bc95ebdef292e82c4b76bc88.zip |
chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/samsung/stumpy/chromeos.c')
-rw-r--r-- | src/mainboard/samsung/stumpy/chromeos.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 5f2a062065d6..96d2b125d791 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -132,3 +133,14 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} |