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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-10 02:52:42 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-12 19:15:47 +0100 |
| commit | d2990c90fd89ee4618a14752f41afe848b27d3e3 (patch) | |
| tree | 61bb9f4386d830ed80e75b8208a1c45f9706a072 /src/mainboard/samsung/stumpy/romstage.c | |
| parent | b2ad8108abe1e91603938610e2fd7b333b944c8a (diff) | |
| download | coreboot-d2990c90fd89ee4618a14752f41afe848b27d3e3.tar.gz coreboot-d2990c90fd89ee4618a14752f41afe848b27d3e3.tar.bz2 coreboot-d2990c90fd89ee4618a14752f41afe848b27d3e3.zip | |
stumpy: Add native raminit support
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13662
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/samsung/stumpy/romstage.c')
| -rw-r--r-- | src/mainboard/samsung/stumpy/romstage.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 87528af5cacb..ab1cb76b78fd 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,6 +31,7 @@ #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -203,6 +204,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 1, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 1, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ +}; + void mainboard_early_init(int s3resume) { init_bootmode_straps(); |