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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-03-29 00:44:51 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-04-06 09:31:25 +0000 |
| commit | 740eee5eec2a978192e8b74327cb96b735b7d0ed (patch) | |
| tree | 1733aab1727e8ddb24f688763de31c3334c0bfdb /src/mainboard/samsung | |
| parent | e50bb8fc9efe25edf1ab27c7b6a88dfb7293ce06 (diff) | |
| download | coreboot-740eee5eec2a978192e8b74327cb96b735b7d0ed.tar.gz coreboot-740eee5eec2a978192e8b74327cb96b735b7d0ed.tar.bz2 coreboot-740eee5eec2a978192e8b74327cb96b735b7d0ed.zip | |
ChromeOS: Drop filling ECFW_RW/RO state in CNVS
This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.
This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.
Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/samsung')
| -rw-r--r-- | src/mainboard/samsung/lumpy/chromeos.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 1b9c7c46f3bd..f8b0afc3a629 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -85,11 +85,6 @@ void init_bootmode_straps(void) pci_s_write_config32(dev, SATA_SP, flags); } -bool mainboard_ec_running_ro(void) -{ - return !ec_read(0xcb); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), |