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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-07-17 10:35:00 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-07-18 11:46:50 +0000 |
| commit | 2c7d1848856ce7bd8539ed4af460a476c39ff2fb (patch) | |
| tree | 1034d2ac269307698ae5548b8f658c4833106173 /src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c | |
| parent | 7815c074b4689d858fde7c8e02153c40de79645e (diff) | |
| download | coreboot-2c7d1848856ce7bd8539ed4af460a476c39ff2fb.tar.gz coreboot-2c7d1848856ce7bd8539ed4af460a476c39ff2fb.tar.bz2 coreboot-2c7d1848856ce7bd8539ed4af460a476c39ff2fb.zip | |
mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings
Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 91a30bfe0efa..dd9736401a9d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -47,12 +47,12 @@ static const struct pad_config gpio_table[] = { /* SDIO -- unused */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ - PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ + PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ - PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ - PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ - PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ + PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */ /* SDCARD */ /* Pull down clock by 20K. */ @@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */ PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ @@ -173,7 +173,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ /* DDI[0:1]_HPD -- unused */ - PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_199, DN_20K, DEEP), /* XHPD_DP */ PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ /* MDSI signals -- unused */ @@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* PMIC Signals unused signals related to an old PMIC interface. */ - PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ |