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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-04-27 11:40:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-02 21:53:03 +0000 |
| commit | 45f449416d3929a875bff76c9ee534ca9aac9dcc (patch) | |
| tree | 1dc8031f2f1f4f7a09c3e7567b189a0a86691f3d /src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | |
| parent | 0e351c9607290b72bd024ceef69afe848e0ed6d5 (diff) | |
| download | coreboot-45f449416d3929a875bff76c9ee534ca9aac9dcc.tar.gz coreboot-45f449416d3929a875bff76c9ee534ca9aac9dcc.tar.bz2 coreboot-45f449416d3929a875bff76c9ee534ca9aac9dcc.zip | |
mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data
hold time on mainboard level to get a proper timing which takes the bus
load into account. Giving these values the driver computes the needed
timings correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index bc70674d6943..336d6c483754 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -41,6 +41,16 @@ chip soc/intel/apollolake # Enable Vtd feature register "enable_vtd" = "1" + # I2C3 controller used for RTC + register "common_soc_config" = "{ + .i2c[3] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 60, + .fall_time_ns = 20, + .data_hold_time_ns = 300 + }, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF |