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| author | Patrick Georgi <patrick@georgi-clan.de> | 2015-09-05 20:21:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-29 10:27:00 +0100 |
| commit | ce2564ac519fd974eeaa070ccb30d5a12e0c3334 (patch) | |
| tree | 03be9390f1ce681e8b3f70a3d09daf4515faa4d2 /src/mainboard/tyan/s2881/get_bus_conf.c | |
| parent | 6fecb7106ef6846e7f75cff59b8d2f9d7ed1109a (diff) | |
| download | coreboot-ce2564ac519fd974eeaa070ccb30d5a12e0c3334.tar.gz coreboot-ce2564ac519fd974eeaa070ccb30d5a12e0c3334.tar.bz2 coreboot-ce2564ac519fd974eeaa070ccb30d5a12e0c3334.zip | |
smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG
This mitigates the Memory Sinkhole issue (described on
https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and
crashing the system explicitly if LAPIC overlaps ASEG.
This needs to happen without a data access (only code fetches) because
data accesses could be tampered with.
Don't try to recover because, if somebody tried to do shenanigans like
these, we have to expect more.
Sandybridge is safe because it does the same test in hardware, and
crashes. Newer chipsets presumably do the same.
This needs to be extended to deal with overlapping TSEG as well.
Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11519
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/tyan/s2881/get_bus_conf.c')
0 files changed, 0 insertions, 0 deletions