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author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 15:50:13 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2022-08-14 10:53:47 +0000 |
commit | 29e71b1291bd22366d75b4dc3c897b355ff268ce (patch) | |
tree | 21fe08ac0057cdbf839b0f8a2f9d440e834c6900 /src/mainboard | |
parent | 2a90e396fc1b0d008024cff1a1b02ee8f1cd0036 (diff) | |
download | coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.gz coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.tar.bz2 coreboot-29e71b1291bd22366d75b4dc3c897b355ff268ce.zip |
broadwell: Move some MRC/refcode settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard')
19 files changed, 10 insertions, 28 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 39c6554f1e2e..3e2f28914563 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "ec_present" = "true" + device cpu_cluster 0 on chip cpu/intel/haswell register "s0ix_enable" = "1" diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index b157fcdf8054..866ea3a56c0c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index b157fcdf8054..866ea3a56c0c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index ad8e50c4b61e..75bf8ee20fd6 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -9,6 +9,8 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" + register "dq_pins_interleaved" = "true" + device cpu_cluster 0 on chip cpu/intel/haswell register "s0ix_enable" = "0" diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index fb9fc09a8c3f..e185d7ea79d4 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: Side USB3.0 port, USB3S1 */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_INTERNAL); /* P1: Rear USB3.0 port, USB3R1 */ diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 571aaafd3370..78765148a6c0 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -11,5 +11,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; /* Enable 2x refresh mode */ pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; } diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index b157fcdf8054..866ea3a56c0c 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index 663dd359e988..10862e86656c 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: Port B, CN01 (IOBoard) */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL); /* P1: Port A, CN01 */ diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 4ef45ee10ce2..b0d9803622bf 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -18,8 +18,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { 2, 0, 1, 3, 6, 4, 7, 5 }, { 2, 1, 0, 3, 6, 5, 4, 7 } }; - pei_data->ec_present = 1; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index e972baabafdf..2f2fa4a44391 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,6 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "dq_pins_interleaved" = "true" + device cpu_cluster 0 on chip cpu/intel/haswell device lapic 0 on end diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 6446a937e1bf..2a9f6b19202d 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -10,5 +10,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; // Enable 2x refresh mode pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; } diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 3a00414d0188..e8726993c7c8 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, USB_PORT_MINI_PCIE); /* P1: Port A, CN22 */ diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 566b9ad6eeff..558d735864a3 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 0; - /* P0: VP8 */ pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: Port 3, USB3 */ diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index e8a03a3f6b95..60a06f47c20e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -9,6 +9,8 @@ chip soc/intel/broadwell # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "ec_present" = "true" + register "panel_cfg" = "{ .up_delay_ms = 200, .down_delay_ms = 50, diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index 00256171460f..04fb9ea9e1b0 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -11,8 +11,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P1: Left Side Port (USB2 only) */ pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); /* P2: Right Side Port (USB2) */ diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index d88c19c26ace..76737cc5e299 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,5 +1,7 @@ chip soc/intel/broadwell + register "dq_pins_interleaved" = "true" + device domain 0 on chip soc/intel/broadwell/pch # Port 0 is HDD diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index 1cb7e756e761..209cf30248f1 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) { - pei_data->dq_pins_interleaved = 1; - /* One DIMM slot */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; @@ -14,8 +12,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P1: Right Side Port (USB2) */ pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); /* P2: Right Side Port (USB2) */ |