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| author | Shelley Chen <shchen@google.com> | 2024-01-07 23:01:38 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2024-01-09 07:50:33 +0000 |
| commit | 3738e7408d6b12fcc4e29aeda5973e632198a344 (patch) | |
| tree | a1535a7ba60f45efa5c04f99ef16c1babe22f533 /src/mainboard | |
| parent | 0acae97863cb842a8a6a56cb0290596510910a8b (diff) | |
| download | coreboot-3738e7408d6b12fcc4e29aeda5973e632198a344.tar.gz coreboot-3738e7408d6b12fcc4e29aeda5973e632198a344.tar.bz2 coreboot-3738e7408d6b12fcc4e29aeda5973e632198a344.zip | |
mb/google/brox: Fix error in DDR DQS config
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what
was in the schematics. Correcting the mistake in this CL.
BUG=b:311450057,b:300690448
BRANCH=None
TEST=tested on device and it passed memory training
Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/memory.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c index 4b03e21423fb..05434b1bef05 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c @@ -53,7 +53,7 @@ static const struct mb_cfg baseboard_memcfg = { .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, |