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| author | Deomid "rojer" Ryabkov <rojer9@fb.com> | 2021-02-03 17:46:29 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-07 21:55:09 +0000 |
| commit | 2085d6f46ad54d7148de38ddd0d183911c2732cc (patch) | |
| tree | 08e1fa14216c32589a55aef32f666d6ca0537d52 /src/mainboard | |
| parent | 1474ddb722d131d1534c958dbb7136e73a34268f (diff) | |
| download | coreboot-2085d6f46ad54d7148de38ddd0d183911c2732cc.tar.gz coreboot-2085d6f46ad54d7148de38ddd0d183911c2732cc.tar.bz2 coreboot-2085d6f46ad54d7148de38ddd0d183911c2732cc.zip | |
Apply locked MSR check to all BDW-DE platforms
It was initially applied to Wedge100 and MonoLake in CB:30290
and the issue has now been observed on Watson as well.
Original change: [CB:30290][commit 817994c1be]
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ocp/monolake/romstage.c | 18 | ||||
| -rw-r--r-- | src/mainboard/ocp/wedge100s/romstage.c | 22 |
2 files changed, 1 insertions, 39 deletions
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index ef41b7720e19..ebc43de8233e 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -19,9 +19,6 @@ #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <drivers/vpd/vpd.h> -#include <cpu/x86/msr.h> -#include <cf9_reset.h> -#include <console/console.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> @@ -193,20 +190,7 @@ static const struct gpio_config gpio_tables[] = { */ void early_mainboard_romstage_entry(void) { - /* - * Sometimes the system boots in an invalid state, where random values - * have been written to MSRs and then the MSRs are locked. - * Seems to always happen on warm reset. - * - * Power cycling or a board_reset() isn't sufficient in this case, so - * issue a full_reset() to "fix" this issue. - */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if (msr.lo & 1) { - console_init(); - printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); - full_reset(); - } + } /** diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 108d7a1c4d99..b1f8f2679686 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -17,9 +17,6 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> -#include <cpu/x86/msr.h> -#include <cf9_reset.h> -#include <console/console.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> @@ -44,25 +41,6 @@ void early_mainboard_romstage_entry(void) if (CONFIG(CONSOLE_SERIAL)) ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - - /* - * Sometimes the system boots in an invalid state, where random values - * have been written to MSRs and then the MSRs are locked. - * Seems to always happen on warm reset. - * - * Power cycling or a board_reset() isn't sufficient in this case, so - * issue a full_reset() to "fix" this issue. - * - * It seems to be a deficiency in the reset logic, as other - * FSP broadwell DE boards are not affected. - */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if (msr.lo & 1) { - console_init(); - printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); - full_reset(); - } } /** |