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| author | Raul E Rangel <rrangel@chromium.org> | 2021-06-09 13:36:10 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-12 12:30:33 +0000 |
| commit | 3acc515bef73c0dfa187a1397135aa9fb36bf2a5 (patch) | |
| tree | 30caeb3eb226ad24492c3774903dead276e808fb /src/mainboard | |
| parent | c4ca2f63967c3ab274d068d50f98df584014101a (diff) | |
| download | coreboot-3acc515bef73c0dfa187a1397135aa9fb36bf2a5.tar.gz coreboot-3acc515bef73c0dfa187a1397135aa9fb36bf2a5.tar.bz2 coreboot-3acc515bef73c0dfa187a1397135aa9fb36bf2a5.zip | |
soc/amd/{cezanne,common}: Enable IOMMU PCIe Device
This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index cf0f51535fb4..30ebe62ef437 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -186,6 +186,8 @@ chip soc/amd/cezanne }" device domain 0 on + device ref iommu on end + device ref gpp_bridge_0 on chip drivers/wifi/generic register "wake" = "GEVENT_8" |