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| author | ariel fang <ariel_fang@wistron.corp-partner.google.com> | 2021-07-19 15:53:49 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-21 20:44:19 +0000 |
| commit | 88c5f9027581048695f96b8e2bdc73b2c2174ee8 (patch) | |
| tree | 328fd726a8f53c6ab87189a8ceb59f1b1ae4b365 /src/mainboard | |
| parent | ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8 (diff) | |
| download | coreboot-88c5f9027581048695f96b8e2bdc73b2c2174ee8.tar.gz coreboot-88c5f9027581048695f96b8e2bdc73b2c2174ee8.tar.bz2 coreboot-88c5f9027581048695f96b8e2bdc73b2c2174ee8.zip | |
mb/google/brya/variants/primus: Update two GPIOs
1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function.
2. Set GPP_E21 as NC to remove LCLW_DET function
BUG=b:190643562
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/gpio.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 21ffedfaacb6..d07dd0e83337 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -27,8 +27,8 @@ static const struct pad_config override_gpio_table[] = { /* C4 : SML0DATA ==> NC */ PAD_NC(GPP_C4, NONE), - /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ + PAD_CFG_GPO(GPP_D3, 1, PLTRST), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D6 : SRCCLKREQ1# ==> NC */ @@ -48,6 +48,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_E17, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E21 : USB_C1_LSX_SOC_RX_STRAP ==> NC */ + PAD_NC(GPP_E21, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |