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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-20 14:07:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-22 09:40:57 +0000 |
| commit | 8dd1a54f0922a8cc600c8fc943dcb4ed5516803b (patch) | |
| tree | 91156ccef0d5a733e662db30a4f455e906acf1eb /src/mainboard | |
| parent | 3ee18cefa3e8a33720e9f62c4034f9fa76789105 (diff) | |
| download | coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.tar.gz coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.tar.bz2 coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.zip | |
mb/siemens/mc_ehl1: Adjust PCIe settings in devicetree
This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.
Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index ec0fe5ac87c6..4da94d9734e2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -50,18 +50,18 @@ chip soc/intel/elkhartlake register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x06" - register "PcieClkSrcUsage[2]" = "0x04" + register "PcieClkSrcUsage[1]" = "0x01" + register "PcieClkSrcUsage[2]" = "0x02" register "PcieClkSrcUsage[3]" = "0xFF" register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcClkReq[0]" = "0x0" - register "PcieClkSrcClkReq[1]" = "0x1" - register "PcieClkSrcClkReq[2]" = "0x2" - register "PcieClkSrcClkReq[3]" = "0x3" - register "PcieClkSrcClkReq[4]" = "0x4" - register "PcieClkSrcClkReq[5]" = "0x5" + register "PcieClkSrcClkReq[0]" = "0xFF" + register "PcieClkSrcClkReq[1]" = "0xFF" + register "PcieClkSrcClkReq[2]" = "0xFF" + register "PcieClkSrcClkReq[3]" = "0xFF" + register "PcieClkSrcClkReq[4]" = "0xFF" + register "PcieClkSrcClkReq[5]" = "0xFF" # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "1" |