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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-22 17:46:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-23 18:03:24 +0000 |
| commit | 9a98fc9d1d40f5bd58e587f81cdb38a482a0a91f (patch) | |
| tree | 62dc89df1b73c91b390d4f0256463574bf731198 /src/mainboard | |
| parent | f66e781336e992f0791480bd710ef32b71d4ad52 (diff) | |
| download | coreboot-9a98fc9d1d40f5bd58e587f81cdb38a482a0a91f.tar.gz coreboot-9a98fc9d1d40f5bd58e587f81cdb38a482a0a91f.tar.bz2 coreboot-9a98fc9d1d40f5bd58e587f81cdb38a482a0a91f.zip | |
soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fch
Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/padmelon/bootblock/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index 13e050d62879..d8c462d17a19 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -31,7 +31,7 @@ static void enable_serial(unsigned int base_port, unsigned int io_enable) void bootblock_mainboard_early_init(void) { - sb_clk_output_48Mhz(2); + fch_clk_output_48Mhz(2); /* * UARTs enabled by default at reset, just need RTS, CTS * and access to the IO address. |