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| author | Bora Guvendik <bora.guvendik@intel.com> | 2021-03-01 14:32:16 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:29:56 +0000 |
| commit | 9d4d2d014c91e041cf7fb8ea593364c6644dd644 (patch) | |
| tree | 7aeb0a44ac8d449248d70666d620d16117272254 /src/mainboard | |
| parent | 011e1b3fbc4d31feaa19ef34d3093f2d289357eb (diff) | |
| download | coreboot-9d4d2d014c91e041cf7fb8ea593364c6644dd644.tar.gz coreboot-9d4d2d014c91e041cf7fb8ea593364c6644dd644.tar.bz2 coreboot-9d4d2d014c91e041cf7fb8ea593364c6644dd644.zip | |
mb/intel/tglrvp: Enable RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.
BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.
Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 8 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 637afab3e2e1..ce7c3d96a56c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -288,7 +288,13 @@ chip soc/intel/tigerlake device pci 1c.0 off end # RP1 0xA0B8 device pci 1c.1 off end # RP2 0xA0B9 device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end # RP4 0xA0BB device pci 1c.4 off end # RP5 0xA0BC device pci 1c.5 off end # RP6 0xA0BD device pci 1c.6 off end # RP7 0xA0BE diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 83b924e7b251..47ac01e57159 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -292,7 +292,13 @@ chip soc/intel/tigerlake device pci 1c.0 off end # RP1 0xA0B8 device pci 1c.1 off end # RP2 0xA0B9 device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end # RP4 0xA0BB device pci 1c.4 off end # RP5 0xA0BC device pci 1c.5 off end # RP6 0xA0BD device pci 1c.6 off end # RP7 0xA0BE |