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| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2023-01-04 10:15:00 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-05 17:56:55 +0000 |
| commit | adec2e6c45fdbf3f2e1d7cde06ed09d00e6c6dff (patch) | |
| tree | 8cb1cd2efeb19122eb752158d0a19cc66ee5b8e6 /src/mainboard | |
| parent | 81016b5c249cd3c16f18a9688074f7e11d3a014d (diff) | |
| download | coreboot-adec2e6c45fdbf3f2e1d7cde06ed09d00e6c6dff.tar.gz coreboot-adec2e6c45fdbf3f2e1d7cde06ed09d00e6c6dff.tar.bz2 coreboot-adec2e6c45fdbf3f2e1d7cde06ed09d00e6c6dff.zip | |
mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
the FSP log.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 1d50bd5b0b6d..b4e7c467f54e 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -99,6 +99,9 @@ chip soc/amd/mendocino register "stt_skin_temp_apu_F" = "0x3200" device domain 0 on + + register "dxio_tx_vboost_enable" = "1" + device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device |