All these boards already had the CACHE_AS_RAM option in their individual

configs. I just moved it the the CPU that they all use.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

13 files changed, 0 insertions, 13 deletions

diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig
index b973c9dad82e..e1b94e9011ab 100644
--- a/src/mainboard/amd/db800/Kconfig
+++ b/src/mainboard/amd/db800/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig
index 6c65f4de1a42..3dc214f00d63 100644
--- a/src/mainboard/amd/norwich/Kconfig
+++ b/src/mainboard/amd/norwich/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
index 9dfb0ca72a8d..52669294f70e 100644
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ b/src/mainboard/artecgroup/dbe61/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig
index f98101b03a83..a082b1fe01cd 100644
--- a/src/mainboard/digitallogic/msm800sev/Kconfig
+++ b/src/mainboard/digitallogic/msm800sev/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
index 7bef792a0b29..a6f512663391 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig
index b30b8bba45f1..027988f95965 100644
--- a/src/mainboard/lippert/hurricane-lx/Kconfig
+++ b/src/mainboard/lippert/hurricane-lx/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	# Board is equipped with a 1 MB SPI flash, however, due to limitations
 	# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 	select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig
index 4f4b28902ca6..482f571e8da5 100644
--- a/src/mainboard/lippert/literunner-lx/Kconfig
+++ b/src/mainboard/lippert/literunner-lx/Kconfig
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	# Board is equipped with a 1 MB SPI flash, however, due to limitations
 	# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 	select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig
index ef6171fa50a8..44326d193f14 100644
--- a/src/mainboard/lippert/roadrunner-lx/Kconfig
+++ b/src/mainboard/lippert/roadrunner-lx/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	# Standard chip is a 512 KB FWH. Replacing it with a 1 MB
 	# SST 49LF008A is possible.
 	select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig
index 89a52ae1a6c4..7526d1ecb437 100644
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig
+++ b/src/mainboard/lippert/spacerunner-lx/Kconfig
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	# Board is equipped with a 1 MB SPI flash, however, due to limitations
 	# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 	select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig
index 395df75eb21f..b10095c90272 100644
--- a/src/mainboard/pcengines/alix1c/Kconfig
+++ b/src/mainboard/pcengines/alix1c/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index bd363f3407cb..bb54d1cad118 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index c1d1af41a05d..1c85149671d4 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_1024
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig
index df6db01198f0..1ec56929d50d 100644
--- a/src/mainboard/winent/pl6064/Kconfig
+++ b/src/mainboard/winent/pl6064/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR