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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2022-07-21 14:11:59 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-13 16:43:45 +0000 |
| commit | 6908e31ce689e3b6dbb5f698b07f41a708c53fbd (patch) | |
| tree | 000ff5d36dbd74773c8041cb9a239b0b6d4af4e8 /src/mainboard | |
| parent | caa5f59279e0c0f49cfe18290abc11b5f3af72c3 (diff) | |
| download | coreboot-6908e31ce689e3b6dbb5f698b07f41a708c53fbd.tar.gz coreboot-6908e31ce689e3b6dbb5f698b07f41a708c53fbd.tar.bz2 coreboot-6908e31ce689e3b6dbb5f698b07f41a708c53fbd.zip | |
Revert "mb/google/brya: Set EPP to 45% for all Brya variants"
This reverts commit 938f33e9f7756d730a1da278679087476a476bf2.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BRANCH=firmware-brya-14505.B
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Icacc555e62533ced30db83e0a036db1c85c0bfa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b8349124ca74..b6ede38cd99c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -122,10 +122,6 @@ chip soc/intel/alderlake }, }" - # set EPP to 45%: 45 * 256/100 = 115 = 0x73 - register "enable_energy_perf_pref" = "true" - register "energy_perf_pref_value" = "0x73" - device domain 0 on device ref igpu on end device ref dtt on end |