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| author | Raul E Rangel <rrangel@chromium.org> | 2022-08-10 15:28:15 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-08-15 16:41:53 +0000 |
| commit | d1a42b6fa92ed2c6a03e7a9ad8bbfd9fe8988e91 (patch) | |
| tree | 60de737737201d442ab56e7df23094b3e88c3fec /src/mainboard | |
| parent | f8a187fcd51dc3a2f4213410293cbb89e214910e (diff) | |
| download | coreboot-d1a42b6fa92ed2c6a03e7a9ad8bbfd9fe8988e91.tar.gz coreboot-d1a42b6fa92ed2c6a03e7a9ad8bbfd9fe8988e91.tar.bz2 coreboot-d1a42b6fa92ed2c6a03e7a9ad8bbfd9fe8988e91.zip | |
mb/google/guybrush: Pass in Cr50 IRQ to PSP
Different guybrush boards have different TPM IRQs. This change passes in
the correct GPIO to the TPM.
BUG=b:241824257
TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test
passes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I61954fa4493fd56e528b616ca65166a31917f557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/guybrush/mainboard.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index cab570672d89..f6f7ccb81d46 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -4,9 +4,11 @@ #include <acpi/acpigen.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/psp.h> #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> +#include <drivers/i2c/tpm/chip.h> #include <gpio.h> #include <soc/acpi.h> #include <variant/ec.h> @@ -115,11 +117,22 @@ void __weak variant_devtree_update(void) { } +static void configure_psp_tpm_gpio(void) +{ + const struct device *cr50_dev = DEV_PTR(cr50); + struct drivers_i2c_tpm_config *cfg = config_of(cr50_dev); + + psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]); +} + static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); mainboard_ec_init(); variant_devtree_update(); + + /* Run this after variant_devtree_update so the IRQ is correct. */ + configure_psp_tpm_gpio(); } static void mainboard_write_blken(void) |