nb/amdk8: Link coherent_ht.c

Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 21 insertions, 10 deletions

diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc
index 019f38ed9270..c6b1ac6792bb 100644
--- a/src/northbridge/amd/amdk8/Makefile.inc
+++ b/src/northbridge/amd/amdk8/Makefile.inc
@@ -12,6 +12,7 @@ romstage-y += raminit_f.c
 endif
 
 romstage-y += reset_test.c
+romstage-y += coherent_ht.c
 
 # Enable this if you want to check the values of the PCI routing registers.
 # Call show_all_routes() anywhere amdk8.h is included.
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index bc03b4cfd720..e335a984f785 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -15,10 +15,22 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
+#define NODE_HT(x) PCI_DEV(0,24+x,0)
+#define NODE_MP(x) PCI_DEV(0,24+x,1)
+#define NODE_MC(x) PCI_DEV(0,24+x,3)
+
+
 #ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);
 void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base);
 void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
+int optimize_link_coherent_ht(void);
+unsigned int get_nodes(void);
+#if CONFIG_RAMINIT_SYSINFO
+void setup_coherent_ht_domain(void);
+#else
+int setup_coherent_ht_domain(void);
+#endif
 #endif
 
 void set_bios_reset(void);
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 464375f2c54e..10ca6ee01391 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -63,11 +63,14 @@
 			CPU1-------------CPU0
  */
 
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include <lib.h>
 #include <stdlib.h>
+#include <stdint.h>
 #include <arch/io.h>
 #include <pc80/mc146818rtc.h>
 #if CONFIG_HAVE_OPTION_TABLE
@@ -78,10 +81,6 @@
 
 #define enable_bsp_routing()	enable_routing(0)
 
-#define NODE_HT(x) PCI_DEV(0,24+x,0)
-#define NODE_MP(x) PCI_DEV(0,24+x,1)
-#define NODE_MC(x) PCI_DEV(0,24+x,3)
-
 #define DEFAULT 0x00010101	/* default row entry */
 
 
@@ -1703,12 +1702,12 @@ static int optimize_link_read_pointers(unsigned nodes)
 	return needs_reset;
 }
 
-static inline unsigned get_nodes(void)
+unsigned int get_nodes(void)
 {
 	return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
 }
 
-static int optimize_link_coherent_ht(void)
+int optimize_link_coherent_ht(void)
 {
 	int needs_reset = 0;
 
@@ -1772,9 +1771,9 @@ static int optimize_link_coherent_ht(void)
 }
 
 #if CONFIG_RAMINIT_SYSINFO
-static void setup_coherent_ht_domain(void)
+void setup_coherent_ht_domain(void)
 #else
-static int setup_coherent_ht_domain(void)
+int setup_coherent_ht_domain(void)
 #endif
 {
 	unsigned nodes;
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index b72bf298354a..d65af9619606 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -7,6 +7,7 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include <lib.h>
+#include "amdk8.h"
 
 // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
 #ifndef K8_ALLOCATE_MMIO_RANGE
@@ -649,8 +650,6 @@ static int ht_setup_chains(uint8_t ht_c_num)
 
 }
 
-static inline unsigned get_nodes(void);
-
 #if CONFIG_RAMINIT_SYSINFO
 static void ht_setup_chains_x(struct sys_info *sysinfo)
 #else