src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

7 files changed, 20 insertions, 19 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index da803ff6276a..7421c18a6921 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2346,7 +2346,7 @@ void set_2t_configuration(struct MCTStatStruc *pMCTstat,
 			enable_slow_access_mode = 1;
 	}
 
-	reg = 0x94; 				/* DRAM Configuration High */
+	reg = 0x94;				/* DRAM Configuration High */
 	dword = Get_NB32_DCT(dev, dct, reg);
 	if (enable_slow_access_mode)
 		dword |= (0x1 << 20);		/* Set 2T CMD mode */
@@ -2539,7 +2539,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat,
 	uint32_t dword;
 
 	dword = Get_NB32(pDCTstat->dev_dct, 0x118);
-	dword &= ~(0x1 << 18); 		/* CC6SaveEn = enable */
+	dword &= ~(0x1 << 18);		/* CC6SaveEn = enable */
 	dword |= (enable & 0x1) << 18;
 	Set_NB32(pDCTstat->dev_dct, 0x118, dword);
 }
@@ -7908,10 +7908,11 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
 	 * Solution: From the bug report:
 	 *  1. A software-initiated frequency change should be wrapped into the
 	 *     following sequence :
-	 * 	- a) Disable Compensation (F2[1, 0]9C_x08[30])
-	 * 	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
-	 * 	c) Do frequency change
-	 * 	d) Enable Compensation (F2[1, 0]9C_x08[30])
+	 *	a) Disable Compensation (F2[1, 0]9C_x08[30])
+	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
+	 *	   all the compensation engines
+	 *	c) Do frequency change
+	 *	d) Enable Compensation (F2[1, 0]9C_x08[30])
 	 *  2. A software-initiated Disable Compensation should always be
 	 *     followed by step b) of the above steps.
 	 * Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index d4b37921c43d..a02f49b5c64d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -134,7 +134,7 @@
 #define MemClkFreqVal		((is_fam15h())?7:3)	/* func 2, offset 94h, bit 3 or 7*/
 #define RDqsEn			12	/* func 2, offset 94h, bit 12*/
 #define DisDramInterface	14	/* func 2, offset 94h, bit 14*/
-#define PowerDownEn      	15	/* func 2, offset 94h, bit 15*/
+#define PowerDownEn		15	/* func 2, offset 94h, bit 15*/
 #define DctAccessWrite		30	/* func 2, offset 98h, bit 30*/
 #define DctAccessDone		31	/* func 2, offset 98h, bit 31*/
 #define MemClrStatus		0	/* func 2, offset A0h, bit 0*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index f751733f736b..9b7481717d6e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1102,7 +1102,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
 
 	dword = Get_NB32_DCT(dev, dct, 0x270);
 	dword &= ~(0x7ffff);				/* DataPrbsSeed = 55555 */
-// 	dword |= (0x55555);
+//	dword |= (0x55555);
 	dword |= (0x44443);				/* Use AGESA seed */
 	Set_NB32_DCT(dev, dct, 0x270, dword);
 
@@ -1199,7 +1199,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
 
 	dword = Get_NB32_DCT(dev, dct, 0x270);
 	dword &= ~(0x7ffff);				/* DataPrbsSeed = 55555 */
-// 	dword |= (0x55555);
+//	dword |= (0x55555);
 	dword |= (0x44443);				/* Use AGESA seed */
 	Set_NB32_DCT(dev, dct, 0x270, dword);
 
@@ -1633,7 +1633,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 	uint8_t lane_training_success[MAX_BYTE_LANES];
 	uint8_t dqs_results_array[1024];
 
- 	uint16_t ren_step = 0x40;
+	uint16_t ren_step = 0x40;
 	uint32_t index_reg = 0x98;
 	uint32_t dev = pDCTstat->dev_dct;
 
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 9aad96cfbc80..31c23b944528 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -115,12 +115,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 
 	OB_ECCRedir =  mctGet_NVbits(NV_ECCRedir);		/* ECC Redirection */
 
-	OB_ChipKill = mctGet_NVbits(NV_ChipKill); 		/* ECC Chip-kill mode */
+	OB_ChipKill = mctGet_NVbits(NV_ChipKill);		/* ECC Chip-kill mode */
 	OF_ScrubCTL = 0;					/* Scrub CTL for Dcache, L2, and dram */
 
 	if (!is_fam15h()) {
 		nvbits = mctGet_NVbits(NV_DCBKScrub);
-		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ 	/* Need not adjust */
+		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */	/* Need not adjust */
 		OF_ScrubCTL |= (u32) nvbits << 16;
 
 		nvbits = mctGet_NVbits(NV_L2BKScrub);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index 8a1f7362a899..2bf85622e674 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -40,11 +40,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	/* Set temporary top of memory from Node structure data.
 	 * Adjust temp top of memory down to accommodate 32-bit IO space.
 	 * Bottom40bIO = top of memory, right justified 8 bits
-	 * 	(defines dram versus IO space type)
+	 *	(defines dram versus IO space type)
 	 * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
-	 * 	(defines dram versus IO space type)
+	 *	(defines dram versus IO space type)
 	 * Cache32bTOP = sub 4GB top of WB cacheable memory,
-	 * 	right justified 8 bits
+	 *	right justified 8 bits
 	 */
 
 	val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 984f6041353b..7c3781fb4011 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1002,7 +1002,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
 	}
 	if (!_SSE2) {
 		cr4 = read_cr4();
-		cr4 &= ~(1<<9); 	/* restore cr4.OSFXSR */
+		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
 	}
 
@@ -1505,7 +1505,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	}
 	if (!_SSE2) {
 		cr4 = read_cr4();
-		cr4 &= ~(1<<9); 	/* restore cr4.OSFXSR */
+		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
 	}
 
@@ -1725,7 +1725,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	}
 	if (!_SSE2) {
 		cr4 = read_cr4();
-		cr4 &= ~(1<<9); 	/* restore cr4.OSFXSR */
+		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
 	}
 
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index a351e8dfb54e..84e26eadea94 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -707,7 +707,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
 			 * For now, skip restoration...
 			 */
 			// for (i = 0; i < 8; i++)
-			// 	wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
+			//	wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
 			wrmsr_uint64_t(0x000002ff, data->msr000002ff);
 			wrmsr_uint64_t(0xc0010010, data->msrc0010010);
 			wrmsr_uint64_t(0xc001001a, data->msrc001001a);