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authorElyes HAOUAS <ehaouas@noos.fr>2014-07-27 19:37:31 +0200
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-29 04:40:27 +0200
commit0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch)
treeb97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/intel/e7501
parent081651b6677c64a5f2861d831822b5f8f3517c21 (diff)
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Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel/e7501')
-rw-r--r--src/northbridge/intel/e7501/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index f42bef2db00e..2247a256af11 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -1276,7 +1276,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
/* Trd */
- /* Set to a 7 clock read delay. This is for 133Mhz
+ /* Set to a 7 clock read delay. This is for 133MHz
* with a CAS latency of 2.5 if 2.0 a 6 clock
* delay is good */