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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-17 23:09:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-03-20 18:11:46 +0000 |
| commit | 064c7999ae5bab4a29d4ee299f6a8c6a97a5da66 (patch) | |
| tree | 004529d0b20a9d0281eea4b3bef96b0ba02b7784 /src/northbridge/intel/sandybridge/raminit_mrc.c | |
| parent | 903d9a225e3e0b03824daf6718936851c51e0664 (diff) | |
| download | coreboot-064c7999ae5bab4a29d4ee299f6a8c6a97a5da66.tar.gz coreboot-064c7999ae5bab4a29d4ee299f6a8c6a97a5da66.tar.bz2 coreboot-064c7999ae5bab4a29d4ee299f6a8c6a97a5da66.zip | |
nb/intel/sandybridge: Deduplicate report_memory_config
Use the version from native raminit, as it takes the reference clock
into account.
Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 5b4b46c583d6..6d00afa6cb7e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -126,53 +126,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input_len); } -static const char *ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - -#define ON_OFF(val) (((val) & 1) ? "on" : "off") - -/* Print the memory controller configuration as read from the memory controller registers. */ -static void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); - printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -#undef ON_OFF - /** * Find PEI executable in coreboot filesystem and execute it. * |