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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 01:22:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:29:14 +0000 |
| commit | d9e58dca9e72ca2efa62eab832aad606c9c58fcd (patch) | |
| tree | 565e2a763d0e70c2efcc0ce744599829679a275c /src/northbridge/intel/sandybridge/raminit_mrc.c | |
| parent | a2a9e607b1e92f322da25d0ca23ce565eb2b17d7 (diff) | |
| download | coreboot-d9e58dca9e72ca2efa62eab832aad606c9c58fcd.tar.gz coreboot-d9e58dca9e72ca2efa62eab832aad606c9c58fcd.tar.bz2 coreboot-d9e58dca9e72ca2efa62eab832aad606c9c58fcd.zip | |
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index d6d39a2c6633..8d13e5569986 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -227,9 +227,9 @@ struct mrc_var_data { static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; + pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; + pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; + pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; pei_data->hpet_address = CONFIG_HPET_ADDRESS; pei_data->thermalbase = 0xfed08000; |