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| author | Angel Pons <th3fanbus@gmail.com> | 2021-11-03 17:12:55 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-11-05 05:57:16 +0000 |
| commit | abe5632b67406509fa69cb3a67b5fae6d7e47c05 (patch) | |
| tree | 902a52f8a7d64d19d28fc8994ef867549f3b78f4 /src/northbridge/intel | |
| parent | 5d4f0838d6fe4f28e98701ae96fa4f4fcbbfd177 (diff) | |
| download | coreboot-abe5632b67406509fa69cb3a67b5fae6d7e47c05.tar.gz coreboot-abe5632b67406509fa69cb3a67b5fae6d7e47c05.tar.bz2 coreboot-abe5632b67406509fa69cb3a67b5fae6d7e47c05.zip | |
nb/intel/haswell/northbridge.c: Drop stale comment
This can now be controlled with the `MMCONF_BUS_NUMBER` Kconfig option.
Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 23220976dd9d..9ead46bc98e9 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -34,10 +34,6 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } -/* - * TODO: We could determine how many PCIe buses we need in the bar. - * For now, that number is hardcoded to a max of 64. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, |