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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-10-05 21:54:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-10-08 21:23:08 +0200 |
| commit | 9aeb69447d3839675b2cac51c3e95a4724fd9b0d (patch) | |
| tree | d9b1cc7483a51ab340d6d9fae78a30e562f99767 /src/northbridge/via/cx700/lpc.c | |
| parent | ec2c18ee6068ef6adf6f5be437d7047c91773654 (diff) | |
| download | coreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.tar.gz coreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.tar.bz2 coreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.zip | |
hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/northbridge/via/cx700/lpc.c')
| -rw-r--r-- | src/northbridge/via/cx700/lpc.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 77ab97c145d5..5a9ced02472c 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -32,7 +32,6 @@ #include <stdlib.h> #define ACPI_IO_BASE 0x400 -#define HPET_ADDR 0xfe800000UL static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 }; @@ -229,7 +228,7 @@ static void cx700_set_lpc_registers(struct device *dev) pci_write_config8(dev, 0x40, 0x54); /* Enable HPET timer */ - pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8)); + pci_write_config32(dev, 0x68, (1 << 31) | (CONFIG_HPET_ADDRESS >> 8)); } |