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author | Stefan Reinauer <reinauer@chromium.org> | 2014-12-17 13:59:20 -0800 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:14:45 +0100 |
commit | 295d9e6569413556afeec7835d6e82aab5878516 (patch) | |
tree | 2eb2f542087a33b5138b4649dcbfa44ff387f343 /src/northbridge/via | |
parent | 42874ace62a0fe7b3c54c729e3c57c330449b86b (diff) | |
download | coreboot-295d9e6569413556afeec7835d6e82aab5878516.tar.gz coreboot-295d9e6569413556afeec7835d6e82aab5878516.tar.bz2 coreboot-295d9e6569413556afeec7835d6e82aab5878516.zip |
Drop VIA Epia-N
ROMCC cleanup.
Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7855
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/via')
-rw-r--r-- | src/northbridge/via/Kconfig | 1 | ||||
-rw-r--r-- | src/northbridge/via/Makefile.inc | 1 | ||||
-rw-r--r-- | src/northbridge/via/cn400/Kconfig | 36 | ||||
-rw-r--r-- | src/northbridge/via/cn400/Makefile.inc | 24 | ||||
-rw-r--r-- | src/northbridge/via/cn400/agp.c | 238 | ||||
-rw-r--r-- | src/northbridge/via/cn400/cn400.h | 49 | ||||
-rw-r--r-- | src/northbridge/via/cn400/northbridge.c | 267 | ||||
-rw-r--r-- | src/northbridge/via/cn400/northbridge.h | 26 | ||||
-rw-r--r-- | src/northbridge/via/cn400/raminit.c | 819 | ||||
-rw-r--r-- | src/northbridge/via/cn400/raminit.h | 31 | ||||
-rw-r--r-- | src/northbridge/via/cn400/vga.c | 153 | ||||
-rw-r--r-- | src/northbridge/via/cn400/vlink.c | 245 |
12 files changed, 0 insertions, 1890 deletions
diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig index 9fe6e8dbba61..7b9fa1da9d38 100644 --- a/src/northbridge/via/Kconfig +++ b/src/northbridge/via/Kconfig @@ -1,5 +1,4 @@ source src/northbridge/via/cn700/Kconfig source src/northbridge/via/cx700/Kconfig -source src/northbridge/via/cn400/Kconfig source src/northbridge/via/vx800/Kconfig source src/northbridge/via/vx900/Kconfig diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc index 9c0f4314fc7b..b3d595e9b9c5 100644 --- a/src/northbridge/via/Makefile.inc +++ b/src/northbridge/via/Makefile.inc @@ -1,5 +1,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700 -subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900 diff --git a/src/northbridge/via/cn400/Kconfig b/src/northbridge/via/cn400/Kconfig deleted file mode 100644 index 42fa0968942e..000000000000 --- a/src/northbridge/via/cn400/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ -config NORTHBRIDGE_VIA_CN400 - bool - -# TODO: Values are from the CX700 datasheet, not sure if this matches CN400. -# TODO: What should be the per-chipset default value here? -choice - prompt "Onboard graphics" - default CN400_VIDEO_MB_32MB - depends on NORTHBRIDGE_VIA_CN400 - -# TODO: Disabling onboard graphics is not yet supported in the source code. -config CN400_VIDEO_MB_OFF - bool "Disabled, 0KB" -config CN400_VIDEO_MB_8MB - bool "Enabled, 8MB" -config CN400_VIDEO_MB_16MB - bool "Enabled, 16MB" -config CN400_VIDEO_MB_32MB - bool "Enabled, 32MB" -config CN400_VIDEO_MB_64MB - bool "Enabled, 64MB" -config CN400_VIDEO_MB_128MB - bool "Enabled, 128MB" - -endchoice - -config VIDEO_MB - int - default 0 if CN400_VIDEO_MB_OFF - default 8 if CN400_VIDEO_MB_8MB - default 16 if CN400_VIDEO_MB_16MB - default 32 if CN400_VIDEO_MB_32MB - default 64 if CN400_VIDEO_MB_64MB - default 128 if CN400_VIDEO_MB_128MB - depends on NORTHBRIDGE_VIA_CN400 - diff --git a/src/northbridge/via/cn400/Makefile.inc b/src/northbridge/via/cn400/Makefile.inc deleted file mode 100644 index 667c71a8583d..000000000000 --- a/src/northbridge/via/cn400/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ramstage-y += northbridge.c -ramstage-y += agp.c -ramstage-y += vga.c -ramstage-y += vlink.c diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c deleted file mode 100644 index ece71e0e7d63..000000000000 --- a/src/northbridge/via/cn400/agp.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "northbridge.h" -#include "cn400.h" - -/* This is the main AGP device, and only one used when configured for AGP 2.0 */ -static void agp_init(device_t dev) -{ - u32 reg32; - u8 reg8; - int i, j; - - /* Some of this may not be necessary (should be handled by the OS). */ - printk(BIOS_DEBUG, "Enabling AGP.\n"); - - /* Allow R/W access to AGP registers. */ - pci_write_config8(dev, 0x4d, 0x05); - - /* Setup PCI latency timer. */ - pci_write_config8(dev, 0xd, 0x8); - - /* Write Secondary Vendor Ids */ - pci_write_config32(dev, 0x2C, 0xAA071106); - - /* - * Set to AGP 3.0 Mode, which should theoretically render the rest of - * the registers set here pointless. - */ - pci_write_config8(dev, 0x84, 0x1b); - - /* AGP Request Queue Size */ - pci_write_config8(dev, 0x4a, 0x1f); - - /* - * AGP Hardware Support (default 0xc4) - * 7: AGP SBA Enable (1 to Enable) - * 6: AGP Enable - * 5: Reserved - * 4: Fast Write Enable - * 3: AGP8X Mode Enable - * 2: AGP4X Mode Enable - * 1: AGP2X Mode Enable - * 0: AGP1X Mode Enable - */ - pci_write_config8(dev, 0x4b, 0xc4); - - /* Enable AGP Backdoor */ - pci_write_config8(dev, 0xb5, 0x03); - - /* Set aperture to 128 MB. */ - /* TODO: Use config option, explain how it works. */ - pci_write_config32(dev, 0x94, 0x00010f20); - /* Set GART Table Base Address (31:12). */ - pci_write_config32(dev, 0x98, (0x37b20 << 12)); - /* Set AGP Aperture Base. */ - pci_write_config32(dev, 0x10, 0xe8000008); - - /* NMI/AGPBUSY# Function Select */ - pci_write_config8(dev, 0xbe, 0x80); - - /* AGP Misc Control 1 */ - pci_write_config8(dev, 0xc2, 0x40); - - /* Enable CPU/PMSTR GART Access and DBI function. */ - reg32 = pci_read_config8(dev, 0xbf); - reg32 |= 0x8c; - pci_write_config8(dev, 0xbf, reg32); - - /* Enable AGP Aperture. */ - pci_write_config32(dev, 0x90, 0x0180); - - /* AGP Control */ - pci_write_config8(dev, 0xbc, 0x25); - pci_write_config8(dev, 0xbd, 0xd2); - - /* - * AGP Pad, driving strength, and delay control. All this should be - * constant, seeing as the VGA controller is onboard. - */ - pci_write_config8(dev, 0x40, 0xda); - pci_write_config8(dev, 0x41, 0xca); - pci_write_config8(dev, 0x42, 0x01); - pci_write_config8(dev, 0x43, 0xca); - pci_write_config8(dev, 0x44, 0x04); - - /* AGPC CKG Control */ - pci_write_config8(dev, 0xc0, 0x04); - pci_write_config8(dev, 0xc1, 0x02); - -#ifdef DEBUG_CN400 - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif -} - -static const struct device_operations agp_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = agp_init, - .ops_pci = 0, -}; - -static const struct pci_driver agp_driver __pci_driver = { - .ops = &agp_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_AGP, -}; - -static void agp_bridge_read_resources (device_t dev) -{ - struct resource *res; - - res = new_resource(dev, 1); - res->base = 0xF0000000ULL; - res->size = 0x06000000ULL; - res->limit = 0xffffffffULL; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - res = new_resource(dev, 2); - res->base = 0xB000UL; - res->size = 4096; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - -} -/* - * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the - * config in this device takes presidence. We configure both just to be safe. - */ -static void agp_bridge_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - pci_write_config16(dev, 0x4, 0x0107); - - /* Secondary Bus Number */ - pci_write_config8(dev, 0x19, 0x01); - /* Subordinate Bus Number */ - pci_write_config8(dev, 0x1a, 0x01); - - /* I/O Base */ - pci_write_config8(dev, 0x1c, 0xf0); - - /* I/O Limit */ - pci_write_config8(dev, 0x1d, 0x00); - - /* Memory Base */ - pci_write_config16(dev, 0x20, 0xf400); - - /* Memory Limit */ - pci_write_config16(dev, 0x22, 0xf5f0); - - /* Prefetchable Memory Base */ - pci_write_config16(dev, 0x24, 0xf000); - - /* Prefetchable Memory Limit */ - pci_write_config16(dev, 0x26, 0xf3f0); - - /* Enable VGA Compatible Memory/IO Range */ - pci_write_config8(dev, 0x3e, 0x0e); - - /* AGP Bus Control */ - pci_write_config8(dev, 0x40, 0x83); - pci_write_config8(dev, 0x41, 0xC7); - pci_write_config8(dev, 0x42, 0x02); - pci_write_config8(dev, 0x43, 0x44); - pci_write_config8(dev, 0x44, 0x34); - pci_write_config8(dev, 0x45, 0x72); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - -static const struct device_operations agp_bridge_operations = { - .read_resources = agp_bridge_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = agp_bridge_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver agp_bridge_driver __pci_driver = { - .ops = &agp_bridge_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_BRIDGE, -}; diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h deleted file mode 100644 index 4921bef3c9b4..000000000000 --- a/src/northbridge/via/cn400/cn400.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define DEBUG_CN400 - -/* VGA stuff */ -#define SR_INDEX 0x3c4 -#define SR_DATA 0x3c5 -#define CRTM_INDEX 0x3b4 -#define CRTM_DATA 0x3b5 -#define CRTC_INDEX 0x3d4 -#define CRTC_DATA 0x3d5 - -/* Memory controller registers */ -#define RANK0_END 0x40 -#define RANK1_END 0x41 -#define RANK2_END 0x42 -#define RANK3_END 0x43 - -#define DDR_PAGE_CTL 0x69 -#define DRAM_REFRESH_COUNTER 0x6a -#define DRAM_MISC_CTL 0x6b -#define CH_A_DQS_OUTPUT_DELAY 0x70 -#define CH_A_MD_OUTPUT_DELAY 0x71 - -/* RAM init commands */ -#define RAM_COMMAND_NORMAL (const char) 0x00 -#define RAM_COMMAND_NOP (const char) 0x01 -#define RAM_COMMAND_PRECHARGE (const char) 0x02 -#define RAM_COMMAND_MSR_LOW (const char) 0x03 -#define RAM_COMMAND_CBR (const char) 0x04 -#define RAM_COMMAND_MSR_HIGH (const char) 0x05 diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c deleted file mode 100644 index b79717904782..000000000000 --- a/src/northbridge/via/cn400/northbridge.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <lib.h> -#include <cbmem.h> -#include <cpu/cpu.h> -#include "northbridge.h" -#include "cn400.h" - -static void memctrl_init(device_t dev) -{ - device_t vlink_dev; - u16 reg16; - u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; - int i, j; - - printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n"); - /* vlink mirror */ - vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_CN400_VLINK, 0); - - /* Setup Low Memory Top */ - /* 0x47 == HA(32:25) */ - /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */ - ranks = pci_read_config8(dev, 0x47); - reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0; - - pci_write_config16(dev, 0x84, reg16); - printk(BIOS_SPEW, "Low Top Address = 0x%04X\n", reg16); - - /* Set up the VGA framebuffer size and Base Address */ - /* Note dependencies between agp.c and vga.c and here */ - reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15) | 0xF00; - pci_write_config16(dev, 0xa0, reg16); - - - for (ranks = 0x4b; ranks >= 0x48; ranks--) { - if (pci_read_config8(dev, ranks)) { - ranks -= 0x48; - break; - } - } - if (ranks == 0x47) - ranks = 0x00; - reg16 = 0xaaf0; - reg16 |= ranks; - /* GMINT Misc. FrameBuffer rank */ - pci_write_config16(dev, 0xb0, reg16); - /* AGPCINT Misc. */ - pci_write_config8(dev, 0xb8, 0x08); - - /* Arbritation Counters */ - pci_write_config8(dev, 0xb2, 0xaa); - - /* Write FIFO Setup */ - pci_write_config8(dev, 0xb3, 0x5a); - - /* Graphics control optimisation */ - pci_write_config8(dev, 0xb4, 0x0f); - - /* Shadow RAM */ - pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30; - /* PAGE C, D, E are all read write enable */ - pci_write_config8(dev, 0x80, pagec); - pci_write_config8(dev, 0x81, paged); - pci_write_config8(dev, 0x83, pagee); - /* PAGE F are read/writable */ - shadowreg = pci_read_config8(dev, 0x82); - shadowreg |= pagef; - pci_write_config8(dev, 0x82, shadowreg); - pci_write_config8(vlink_dev, 0x61, pagec); - pci_write_config8(vlink_dev, 0x62, paged); - pci_write_config8(vlink_dev, 0x64, pagee); - - shadowreg = pci_read_config8(vlink_dev, 0x63); - shadowreg |= pagef; - pci_write_config8(vlink_dev, 0x63, shadowreg); - - /* Activate VGA Frame Buffer */ - - reg8 = pci_read_config8(dev, 0xA0); - reg8 |= 0x01; - pci_write_config8(dev, 0xA0, reg8); - -#ifdef DEBUG_CN400 - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif - printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__); -} - -static const struct device_operations memctrl_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = memctrl_init, - .ops_pci = 0, -}; - -static const struct pci_driver memctrl_driver __pci_driver = { - .ops = &memctrl_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, -}; - -static void cn400_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk(BIOS_SPEW, "Entering %s.\n", __func__); - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "Leaving %s.\n", __func__); -} - -#ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, - unsigned long base, unsigned long size) -{ - struct resource *res; - - printk(BIOS_SPEW, "Configuring Via C3 LAPIC Fixed Resource\n"); - /* Fixed LAPIC resource */ - res = new_resource(dev, 1); - res->base = (resource_t) base; - res->size = size; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} -#endif - -static void cn400_domain_set_resources(device_t dev) -{ - device_t mc_dev; - u32 pci_tolm; - - printk(BIOS_SPEW, "Entering %s.\n", __func__); - - pci_tolm = find_pci_tolm(dev->link_list); - mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0); - - if (mc_dev) { - unsigned long tomk, tolmk; - unsigned char rambits; - int idx; - - rambits = pci_read_config8(mc_dev, 0x47); - tomk = rambits * 32 * 1024; - /* Compute the Top Of Low Memory (TOLM), in Kb. */ - tolmk = pci_tolm >> 10; - printk(BIOS_SPEW, "tomk is 0x%lx, tolmk is 0x%08lX\n", tomk, tolmk); - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - - /* Locate the High Tables at the Top of Low Memory below the Video RAM */ - set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024); - - /* Report the memory regions. */ - idx = 10; - /* TODO: Hole needed? */ - ram_resource(dev, idx++, 0, 640); /* First 640k */ - /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ - ram_resource(dev, idx++, 768, - (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); - } - assign_resources(dev->link_list); - - printk(BIOS_SPEW, "Leaving %s.\n", __func__); -} - -static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) -{ - printk(BIOS_DEBUG, "Entering %s.\n", __func__); - - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); - return max; -} - -static struct device_operations pci_domain_ops = { - .read_resources = cn400_domain_read_resources, - .set_resources = cn400_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = cn400_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev)); - - /* Set the operations if it is a special bus type. */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_via_cn400_ops = { - CHIP_NAME("VIA CN400 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/via/cn400/northbridge.h b/src/northbridge/via/cn400/northbridge.h deleted file mode 100644 index 1fa848f31df5..000000000000 --- a/src/northbridge/via/cn400/northbridge.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef NORTHBRIDGE_VIA_CN400_H -#define NORTHBRIDGE_VIA_CN400_H - -extern unsigned int cn400_scan_root_bus(device_t root, unsigned int max); - -#endif /* NORTHBRIDGE_VIA_CN400_H */ diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c deleted file mode 100644 index d15a6338e051..000000000000 --- a/src/northbridge/via/cn400/raminit.c +++ /dev/null @@ -1,819 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> - * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - Automatically detect and set up ddr dram on the CN400 chipset. - Assumes DDR400 memory as no attempt is made to clock - the chipset down if slower memory is installed. - So far tested on: - 512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided) -*/ -/* ported from Via VT8263 Code*/ - -#include <spd.h> -#include <delay.h> -#include <cpu/x86/mtrr.h> -#include "cn400.h" - -static void dimm_read(unsigned long bank,unsigned long x) -{ - //unsigned long eax; - volatile unsigned long y; - //eax = x; - y = * (volatile unsigned long *) (x+ bank) ; - -} - - -static void print_val(char *str, int val) -{ - print_debug(str); - print_debug_hex8(val); -} - -/** - * Configure the bus between the CPU and the northbridge. This might be able to - * be moved to post-ram code in the future. For the most part, these registers - * should not be messed around with. These are too complex to explain short of - * copying the datasheets into the comments, but most of these values are from - * the BIOS Porting Guide, so they should work on any board. If they don't, - * try the values from your factory BIOS. - * - * TODO: Changing the DRAM frequency doesn't work (hard lockup). - * - * @param dev The northbridge's CPU Host Interface (D0F2). - */ -static void c3_cpu_setup(device_t dev) -{ - /* Host bus interface registers (D0F2 0x50-0x67) */ - /* Taken from CN700 and updated from running CN400 */ - uint8_t reg8; - - /* Host Bus I/O Circuit (see datasheet) */ - /* Host Address Pullup/down Driving */ - pci_write_config8(dev, 0x70, 0x33); - pci_write_config8(dev, 0x71, 0x44); - pci_write_config8(dev, 0x72, 0x33); - pci_write_config8(dev, 0x73, 0x44); - - /* Output Delay Stagger Control */ - pci_write_config8(dev, 0x74, 0x70); - - /* AGTL+ I/O Circuit */ - pci_write_config8(dev, 0x75, 0x08); - - /* AGTL+ Compensation Status */ - pci_write_config8(dev, 0x76, 0x74); - - /* AGTL+ Auto Compensation Offest */ - pci_write_config8(dev, 0x77, 0x00); - pci_write_config8(dev, 0x78, 0x94); - - /* Request phase control */ - pci_write_config8(dev, 0x50, 0xA8); - - /* Line DRDY# Timing Control */ - pci_write_config8(dev, 0x60, 0x00); - pci_write_config8(dev, 0x61, 0x00); - pci_write_config8(dev, 0x62, 0x00); - - /* QW DRDY# Timing Control */ - pci_write_config8(dev, 0x63, 0x00); - pci_write_config8(dev, 0x64, 0x00); - pci_write_config8(dev, 0x65, 0x00); - - /* Read Line Burst DRDY# Timing Control */ - pci_write_config8(dev, 0x66, 0x00); - pci_write_config8(dev, 0x67, 0x00); - - /* CPU Interface Control */ - pci_write_config8(dev, 0x51, 0xFE); - pci_write_config8(dev, 0x52, 0xEF); - - /* Arbitration */ - pci_write_config8(dev, 0x53, 0x88); - - /* Write Policy & Reorder Latecy */ - pci_write_config8(dev, 0x56, 0x00); - - /* Delivery-Trigger Control */ - pci_write_config8(dev, 0x58, 0x00); - - /* IPI Control */ - pci_write_config8(dev, 0x59, 0x30); - - /* CPU Misc Control */ - pci_write_config8(dev, 0x5C, 0x00); - - /* Write Policy */ - pci_write_config8(dev, 0x5d, 0xb2); - - /* Bandwidth Timer */ - pci_write_config8(dev, 0x5e, 0x88); - - /* CPU Miscellaneous Control */ - pci_write_config8(dev, 0x5f, 0xc7); - - /* CPU Miscellaneous Control */ - pci_write_config8(dev, 0x55, 0x28); - pci_write_config8(dev, 0x57, 0x69); - - /* CPU Host Bus Final Setup */ - reg8 = pci_read_config8(dev, 0x54); - reg8 |= 0x08; - pci_write_config8(dev, 0x54, reg8); - -} - -static void ddr_ram_setup(void) -{ - uint8_t b, c, bank, ma; - uint16_t i; - unsigned long bank_address; - - - print_debug("CN400 RAM init starting\n"); - - pci_write_config8(ctrl.d0f7, 0x75, 0x08); - - - /* No Interleaving or Multi Page */ - pci_write_config8(ctrl.d0f3, 0x69, 0x00); - pci_write_config8(ctrl.d0f3, 0x6b, 0x10); - -/* - DRAM MA Map Type Device 0 Fn3 Offset 50-51 - - Determine memory addressing based on the module's memory technology and - arrangement. See Table 4-9 of Intel's 82443GX datasheet for details. - - Bank 1/0 MA map type 50[7-5] - Bank 1/0 command rate 50[4] - Bank 3/2 MA map type 50[3-1] - Bank 3/2 command rate 50[0] - - - Read SPD byte 17, Number of banks on SDRAM device. -*/ - c = 0; - b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM); - //print_val("Detecting Memory\nNumber of Banks ",b); - - // Only supporting 4 bank chips just now - if( b == 4 ){ - /* Read SPD byte 3, Number of row addresses. */ - c = 0x01; - bank = 0x40; - b = smbus_read_byte(DIMM0, SPD_NUM_ROWS); - //print_val("\nNumber of Rows ", b); - - if( b >= 0x0d ){ // 256/512Mb - - if (b == 0x0e) - bank = 0x48; - else - bank = 0x44; - - /* Read SPD byte 13, Primary DRAM width. */ - b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH); - //print_val("\nPrimary DRAM width", b); - if( b != 4 ) // not 64/128Mb (x4) - c = 0x81; // 256Mb - } - - /* Read SPD byte 4, Number of column addresses. */ - b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS); - //print_val("\nNo Columns ",b); - if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr - if( b == 9 ) c |= 0x40; // 9 bit col addr - if( b == 8 ) c |= 0x20; // 8 bit col addr - - //print_val("\nMA type ", c); - pci_write_config8(ctrl.d0f3, 0x50, c); - - } - - /* Disable Upper Banks */ - pci_write_config8(ctrl.d0f3, 0x51, 0x00); - -/* else - { - die("DRAM module size is not supported by CN400\n"); - } -*/ - -/* - DRAM bank size. See 4.3.1 pg 35 - - 5a->5d set to end address for each bank. 1 bit == 32MB - 5a = bank 0 - 5b = bank 0 + b1 - 5c = bank 0 + b1 + b2 - 5d = bank 0 + b1 + b2 + b3 -*/ - - // Read SPD byte 31 Module bank density - //c = 0; - b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); - if( b & 0x02 ) - { - c = 0x40; // 2GB - bank |= 0x02; - } - else if( b & 0x01) - { - c = 0x20; // 1GB - if (bank == 0x48) bank |= 0x01; - else bank |= 0x03; - } - else if( b & 0x80) - { - c = 0x10; // 512MB - if (bank == 0x44) bank |= 0x02; - } - else if( b & 0x40) - { - c = 0x08; // 256MB - if (bank == 0x44) bank |= 0x01; - else bank |= 0x03; - } - else if( b & 0x20) - { - c = 0x04; // 128MB - if (bank == 0x40) bank |= 0x02; - } - else if( b & 0x10) - { - c = 0x02; // 64MB - bank |= 0x01; - } - else if( b & 0x08) c = 0x01; // 32MB - else c = 0x01; // Error, use default - - // set bank zero size - pci_write_config8(ctrl.d0f3, 0x40, c); - - // SPD byte 5 # of physical banks - b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS); - - //print_val("\nNo Physical Banks ",b); - if( b == 2) - { - c <<=1; - bank |= 0x80; - } -/* else - { - die("Only a single DIMM is supported by EPIA-N(L)\n"); - } -*/ - // set banks 1,2,3... - pci_write_config8(ctrl.d0f3, 0x41,c); - pci_write_config8(ctrl.d0f3, 0x42,c); - pci_write_config8(ctrl.d0f3, 0x43,c); - pci_write_config8(ctrl.d0f3, 0x44,c); - pci_write_config8(ctrl.d0f3, 0x45,c); - pci_write_config8(ctrl.d0f3, 0x46,c); - pci_write_config8(ctrl.d0f3, 0x47,c); - - /* Top Rank Address Mirrored to the South Bridge */ - /* over the VLink */ - pci_write_config8(ctrl.d0f7, 0x57, (c << 1)); - - ma = bank; - - /* Read SPD byte 18 CAS Latency */ - b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); -/* print_debug("\nCAS Supported "); - if(b & 0x04) - print_debug("2 "); - if(b & 0x08) - print_debug("2.5 "); - if(b & 0x10) - print_debug("3"); - - c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - print_val("\nCycle time at CL X (nS)", c); - c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); - print_val("\nCycle time at CL X-0.5 (nS)", c); - c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); - print_val("\nCycle time at CL X-1 (nS)", c); -*/ - /* Scaling of Cycle Time SPD data */ - /* 7 4 3 0 */ - /* ns x0.1ns */ - bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - - if( b & 0x10 ){ // DDR offering optional CAS 3 - //print_debug("\nStarting at CAS 3"); - c = 0x30; - /* see if we can better it */ - if( b & 0x08 ){ // DDR mandatory CAS 2.5 - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5 - //print_debug("\nWe can do CAS 2.5"); - c = 0x20; - } - } - if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2 - //print_debug("\nWe can do CAS 2"); - c = 0x10; - } - } - }else{ // no optional CAS values just 2 & 2.5 - //print_debug("\nStarting at CAS 2.5"); - c = 0x20; // assume CAS 2.5 - if( b & 0x04){ // Should always happen - if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2 - //print_debug("\nWe can do CAS 2"); - c = 0x10; - } - } - } - - /* Scale DRAM Cycle Time to tRP/tRCD */ - /* 7 2 1 0 */ - /* ns x0.25ns */ - if ( bank <= 0x50 ) bank = 0x14; - else if (bank <= 0x60) bank = 0x18; - else bank = 0x1E; - -/* - DRAM Timing Device 0 Fn 3 Offset 56 - - RAS Pulse width 56[7,6] - CAS Latency 56[5,4] - Row pre-charge 56[1,0] - - SDR DDR - 00 1T - - 01 2T 2T - 10 3T 2.5T - 11 - 3T - - RAS/CAS delay 56[3,2] - - Determine row pre-charge time (tRP) - - - Read SPD byte 27, min row pre-charge time. -*/ - - b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME); - - //print_val("\ntRP ",b); - if ( b >= (5 * bank)) { - c |= 0x03; // set tRP = 5T - } - else if ( b >= (4 * bank)) { - c |= 0x02; // set tRP = 4T - } - else if ( b >= (3 * bank)) { - c |= 0x01; // set tRP = 3T - } - -/* - Determine RAS to CAS delay (tRCD) - - Read SPD byte 29, min row pre-charge time. -*/ - - b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY); - //print_val("\ntRCD ",b); - - if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T - else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T - else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T - -/* - Determine RAS pulse width (tRAS) - - - Read SPD byte 30, device min active to pre-charge time. -*/ - - /* tRAS is in whole ns */ - bank = bank >> 2; - - b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - //print_val("\ntRAS ",b); - //print_val("\nBank ", bank); - if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T - else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T - else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T - - /* Write DRAM Timing All Banks I */ - pci_write_config8(ctrl.d0f3, 0x56, c); - - /* TWrite DRAM Timing All Banks II */ - pci_write_config8(ctrl.d0f3, 0x57, 0x1a); - - /* DRAM arbitration timer */ - pci_write_config8(ctrl.d0f3, 0x65, 0x99); - -/* - DRAM Clock Device 0 Fn 3 Offset 68 -*/ - bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - - /* Setup DRAM Cycle Time */ - if ( bank <= 0x50 ) - { - /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */ - /* This sets to 133MHz FSB / DDR400. */ - pci_write_config8(ctrl.d0f3, 0x68, 0x85); - } - else if (bank <= 0x60) - { - /* DRAM DDR Control Alert! Alert! This hardwires to */ - /* 133MHz FSB / DDR333. See also c3_cpu_setup */ - pci_write_config8(ctrl.d0f3, 0x68, 0x81); - } - else - { - /* DRAM DDR Control Alert! Alert! This hardwires to */ - /* 133MHz FSB / DDR266. See also c3_cpu_setup */ - pci_write_config8(ctrl.d0f3, 0x68, 0x80); - } - - /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */ - udelay(200); - -/* - Determine bank interleave - - Read SPD byte 17, Number of banks on SDRAM device. -*/ - c = 0x0F; - b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM); - if( b == 4) c |= 0x80; - else if (b == 2) c |= 0x40; - - /* 4-Way Interleave With Multi-Paging (From Running System)*/ - pci_write_config8(ctrl.d0f3, 0x69, c); - - /*DRAM Controller Internal Options */ - pci_write_config8(ctrl.d0f3, 0x54, 0x01); - - /* DRAM Arbitration Control */ - pci_write_config8(ctrl.d0f3, 0x66, 0x82); - - /* DRAM Control */ - pci_write_config8(ctrl.d0f3, 0x6e, 0x80); - - /* Disable refresh for now */ - pci_write_config8(ctrl.d0f3, 0x6a, 0x00); - - /* DDR Clock Gen Duty Cycle Control */ - pci_write_config8(ctrl.d0f3, 0xEE, 0x01); - - - /* DRAM Clock Control */ - pci_write_config8(ctrl.d0f3, 0x6c, 0x00); - - /* DRAM Bus Turn-Around Setting */ - pci_write_config8(ctrl.d0f3, 0x60, 0x01); - - /* Disable DRAM refresh */ - pci_write_config8(ctrl.d0f3,0x6a,0x0); - - - /* Memory Pads Driving and Range Select */ - pci_write_config8(ctrl.d0f3, 0xe2, 0xAA); - pci_write_config8(ctrl.d0f3, 0xe3, 0x00); - pci_write_config8(ctrl.d0f3, 0xe4, 0x99); - - /* DRAM signal timing control */ - pci_write_config8(ctrl.d0f3, 0x74, 0x99); - pci_write_config8(ctrl.d0f3, 0x76, 0x09); - pci_write_config8(ctrl.d0f3, 0x77, 0x12); - - pci_write_config8(ctrl.d0f3, 0xe0, 0xAA); - pci_write_config8(ctrl.d0f3, 0xe1, 0x00); - pci_write_config8(ctrl.d0f3, 0xe6, 0x00); - pci_write_config8(ctrl.d0f3, 0xe8, 0xEE); - pci_write_config8(ctrl.d0f3, 0xea, 0xEE); - - - /* SPD byte 5 # of physical banks */ - b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1; - c = b | 0x40; - - pci_write_config8(ctrl.d0f3, 0xb0, c); - - /* Set RAM Decode method */ - pci_write_config8(ctrl.d0f3, 0x55, 0x0a); - - /* Enable DIMM Ranks */ - pci_write_config8(ctrl.d0f3, 0x48, ma); - udelay(200); - - c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS); - c &= 0x08; - if ( c == 0x08 ) - { - print_debug("Setting Burst Length 8\n"); - /* - CPU Frequency Device 0 Function 2 Offset 54 - - CPU FSB Operating Frequency (bits 7:5) - 000 : 100MHz 001 : 133MHz - 010 : 200MHz - 011->111 : Reserved - - SDRAM BL8 (4) - - Don't change Frequency from power up defaults - This seems to lockup the RAM interface - */ - c = pci_read_config8(ctrl.d0f2, 0x54); - c |= 0x10; - pci_write_config8(ctrl.d0f2, 0x54, c); - i = 0x008; // Used later to set SDRAM MSR - } - - - for( bank = 0 , bank_address=0; bank <= b ; bank++) { -/* - DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1) -*/ - - /* NOP command enable */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_NOP; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - - /* read a double word from any address of the dimm */ - dimm_read(bank_address,0x1f000); - //udelay(200); - - /* All bank precharge Command Enable */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - dimm_read(bank_address,0x1f000); - - - /* MSR Enable Low DIMM*/ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - /* TODO: Bank Addressing for Different Numbers of Row Addresses */ - dimm_read(bank_address,0x2000); - udelay(1); - dimm_read(bank_address,0x800); - udelay(1); - - /* All banks precharge Command Enable */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - dimm_read(bank_address,0x1f200); - - /* CBR Cycle Enable */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_CBR; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - - /* Read 8 times */ - for (c=0;c<8;c++) { - dimm_read(bank_address,0x1f300); - udelay(100); - } - - /* MSR Enable */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - - -/* - Mode Register Definition - with adjustement so that address calculation is correct - 64 bit technology, therefore - a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented - to DIMM as a row or column address. - - MR[9-7] CAS Latency - MR[6] Burst Type 0 = sequential, 1 = interleaved - MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved - MR[0-2] dont care - - CAS Latency - 000 reserved - 001 reserved - 010 2 - 011 3 - 100 reserved - 101 1.5 - 110 2.5 - 111 reserved - - CAS 2 0101011000 = 0x158 - CAS 2.5 1101011000 = 0x358 - CAS 3 0111011000 = 0x1d8 - -*/ - c = pci_read_config8(ctrl.d0f3, 0x56); - if( (c & 0x30) == 0x10 ) - dimm_read(bank_address,(0x150 + i)); - else if((c & 0x30) == 0x20 ) - dimm_read(bank_address,(0x350 + i)); - else - dimm_read(bank_address,(0x1d0 + i)); - - - /* Normal SDRAM Mode */ - c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); - c &= 0xf8; /* Clear bits 2-0. */ - c |= RAM_COMMAND_NORMAL; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - - bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000; - } // end of for each bank - - - /* Set DRAM DQS Output Control */ - pci_write_config8(ctrl.d0f3, 0x79, 0x11); - - /* Set DQS A/B Input delay to defaults */ - pci_write_config8(ctrl.d0f3, 0x7A, 0xA1); - pci_write_config8(ctrl.d0f3, 0x7B, 0x62); - - /* DQS Duty Cycle Control */ - pci_write_config8(ctrl.d0f3, 0xED, 0x11); - - /* SPD byte 5 # of physical banks */ - b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1; - - /* determine low bond */ - if( b == 2) - bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000; - else - bank_address = 0; - - for(i = 0x30 ; i < 0x0ff; i++){ - pci_write_config8(ctrl.d0f3,0x70,i); - // clear - *(volatile unsigned long*)(0x4000) = 0; - *(volatile unsigned long*)(0x4100+bank_address) = 0; - *(volatile unsigned long*)(0x4200) = 0; - *(volatile unsigned long*)(0x4300+bank_address) = 0; - *(volatile unsigned long*)(0x4400) = 0; - *(volatile unsigned long*)(0x4500+bank_address) = 0; - - // fill - *(volatile unsigned long*)(0x4000) = 0x12345678; - *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567; - *(volatile unsigned long*)(0x4200) = 0x78123456; - *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345; - *(volatile unsigned long*)(0x4400) = 0x56781234; - *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123; - - // verify - if( *(volatile unsigned long*)(0x4000) != 0x12345678) - continue; - - if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567) - continue; - - if( *(volatile unsigned long*)(0x4200) != 0x78123456) - continue; - - if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345) - continue; - - if( *(volatile unsigned long*)(0x4400) != 0x56781234) - continue; - - if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123) - continue; - - // if everything verified then found low bond - break; - - } - print_val("\nLow Bond ",i); - if( i < 0xff ){ - c = i++; - for( ; i <0xff ; i++){ - pci_write_config8(ctrl.d0f3,0x70, i); - // clear - *(volatile unsigned long*)(0x8000) = 0; - *(volatile unsigned long*)(0x8100+bank_address) = 0; - *(volatile unsigned long*)(0x8200) = 0x0; - *(volatile unsigned long*)(0x8300+bank_address) = 0; - *(volatile unsigned long*)(0x8400) = 0x0; - *(volatile unsigned long*)(0x8500+bank_address) = 0; - - // fill - *(volatile unsigned long*)(0x8000) = 0x12345678; - *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567; - *(volatile unsigned long*)(0x8200) = 0x78123456; - *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345; - *(volatile unsigned long*)(0x8400) = 0x56781234; - *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123; - - // verify - if( *(volatile unsigned long*)(0x8000) != 0x12345678) - break; - - if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567) - break; - - if( *(volatile unsigned long*)(0x8200) != 0x78123456) - break; - - if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345) - break; - - if( *(volatile unsigned long*)(0x8400) != 0x56781234) - break; - - if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123) - break; - - } - print_val(" High Bond ",i); - c = ((i - c)<<1)/3 + c; - print_val(" Setting DQS delay",c); - print_debug("\n"); - pci_write_config8(ctrl.d0f3,0x70,c); - }else{ - pci_write_config8(ctrl.d0f3,0x70,0x67); - } - - /* Set DQS ChA Data Output Delay to the default */ - pci_write_config8(ctrl.d0f3, 0x71, 0x65); - - /* Set Ch B DQS Output Delays */ - pci_write_config8(ctrl.d0f3, 0x72, 0x2a); - pci_write_config8(ctrl.d0f3, 0x73, 0x29); - - pci_write_config8(ctrl.d0f3, 0x78, 0x03); - - /* Mystery Value */ - pci_write_config8(ctrl.d0f3, 0x67, 0x50); - - /* Enable Toggle Limiting */ - pci_write_config8(ctrl.d0f4, 0xA3, 0x80); - -/* - DRAM refresh rate Device 0 F3 Offset 6a - TODO :: Fix for different DRAM technologies - other than 512Mb and DRAM Freq - Units of 16 DRAM clock cycles - 1. -*/ - //c = pci_read_config8(ctrl.d0f3, 0x68); - //c &= 0x07; - //b = smbus_read_byte(DIMM0, SPD_REFRESH); - //print_val("SPD_REFRESH = ", b); - - pci_write_config8(ctrl.d0f3,0x6a,0x65); - - /* SMM and APIC decoding, we do not use SMM */ - b = 0x29; - pci_write_config8(ctrl.d0f3, 0x86, b); - /* SMM and APIC decoding mirror */ - pci_write_config8(ctrl.d0f7, 0xe6, b); - - /* Open Up the Rest of the Shadow RAM */ - pci_write_config8(ctrl.d0f3,0x80,0xff); - pci_write_config8(ctrl.d0f3,0x81,0xff); - - /* pci */ - pci_write_config8(ctrl.d0f7,0x70,0x82); - pci_write_config8(ctrl.d0f7,0x73,0x01); - pci_write_config8(ctrl.d0f7,0x76,0x50); - - pci_write_config8(ctrl.d0f7,0x71,0xc8); - - - /* VGA device. */ - pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15)); - pci_write_config16(ctrl.d0f3, 0xa4, 0x0010); - print_debug("CN400 raminit.c done\n"); -} diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h deleted file mode 100644 index 89ea0d686bb1..000000000000 --- a/src/northbridge/via/cn400/raminit.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef RAMINIT_H -#define RAMINIT_H - -#define DIMM_SOCKETS 1 /* Only one works, for now. */ - -struct mem_controller { - device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0; - u8 channel0[DIMM_SOCKETS]; -}; - -#endif diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c deleted file mode 100644 index a2afdce900ec..000000000000 --- a/src/northbridge/via/cn400/vga.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Note: Some of the VGA control registers are located on the memory - * controller. Registers are set both in raminit.c and northbridge.c. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <cpu/cpu.h> -#include <arch/interrupt.h> -#include "northbridge.h" -#include "cn400.h" -#include <x86emu/regs.h> - -static int via_cn400_int15_handler(void) -{ - int res=0; - printk(BIOS_DEBUG, "via_cn400_int15_handler\n"); - switch(X86_EAX & 0xffff) { - case 0x5f19: - break; - case 0x5f18: - X86_EAX=0x5f; - X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - X86_ECX=0x060; - res=1; - break; - case 0x5f00: - X86_EAX = 0x8600; - break; - case 0x5f01: - X86_EAX = 0x5f; - X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 - res = 1; - break; - case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; - break; - case 0x5f0f: - X86_EAX=0x860f; - break; - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); - break; - } - return res; -} - -static void vga_init(device_t dev) -{ - u8 reg8; - - mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler); - - /* Set memory rate to 200 MHz. */ - outb(0x3d, CRTM_INDEX); - reg8 = inb(CRTM_DATA); - reg8 &= 0x0f; - reg8 |= (0x1 << 4); - outb(0x3d, CRTM_INDEX); - outb(reg8, CRTM_DATA); - - /* Set framebuffer size. */ - reg8 = (CONFIG_VIDEO_MB / 4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); - - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x0d, 0x20); - pci_write_config32(dev, 0x10, 0xf0000008); - pci_write_config32(dev, 0x14, 0xf4000000); - - printk(BIOS_DEBUG, "Initializing VGA...\n"); - - pci_dev_init(dev); - - /* It's not clear if these need to be programmed before or after - * the VGA BIOS runs. Try both, clean up later. */ - - /* Set memory rate to 200 MHz (again). */ - outb(0x3d, CRTM_INDEX); - reg8 = inb(CRTM_DATA); - reg8 &= 0x0f; - reg8 |= (0x1 << 4); - outb(0x3d, CRTM_INDEX); - outb(reg8, CRTM_DATA); - - /* Set framebuffer size (again). */ - reg8 = (CONFIG_VIDEO_MB / 4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); - -#ifdef DEBUG_CN400 - int i, j; - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif -} - -static const struct device_operations vga_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .ops_pci = 0, -}; - -static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_VGA, -}; diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c deleted file mode 100644 index 2319e75ac96e..000000000000 --- a/src/northbridge/via/cn400/vlink.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <console/console.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "northbridge.h" -#include "cn400.h" - -static void noop_1k(u32 knops) -{ - u32 i; - - for (i = 0; i < 1024 * knops; i++) { - __asm__ volatile ("nop\n\t"); - } - - return; -} - -/* Vlink Performance Improvements */ -static void vlink_init(device_t dev) -{ - u8 reg, reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - /* Disconnect the VLink Before Changing Settings */ - reg = pci_read_config8(dev, 0x47); - reg |= 0x04; - pci_write_config8(dev, 0x47, reg); - - /* Wait for anything pending to flush */ - noop_1k(20); - - /* Setup Vlink Mode 1 */ - pci_write_config8(dev, 0x4F, 0x01); - pci_write_config8(dev, 0x48, 0x13); - - /* PCI Buffer Control */ - pci_write_config8(dev, 0x70, 0x82); - - /* CPU to PCI Flow Control */ - pci_write_config8(dev, 0x71, 0xc8); - pci_write_config8(dev, 0x72, 0xee); - - /* PCI Master Control */ - pci_write_config8(dev, 0x73, 0x01); - pci_write_config8(dev, 0x74, 0x20); - - /* PCI Arbitration 1 */ - pci_write_config8(dev, 0x75, 0x0f); - - /* PCI Arbitration 2 */ - pci_write_config8(dev, 0x76, 0x50); - pci_write_config8(dev, 0x77, 0x6e); - pci_write_config8(dev, 0x7F, 0x10); - - pci_write_config8(dev, 0x94, 0x20); - pci_write_config8(dev, 0x95, 0x0f); - - /* V-Link CKG Control 1 */ - pci_write_config8(dev, 0xB0, 0x01); - - /* V-Link NB Compensation Control */ - pci_write_config8(dev, 0xB5, 0x46); - pci_write_config8(dev, 0xB6, 0x68); - reg = pci_read_config8(dev, 0xB4); - reg |= 0x01; - pci_write_config8(dev, 0xB4, reg); - - /* V-Link NB Receive Strobe Delay */ - pci_write_config8(dev, 0xB7, 0x02); - - /* V-Link SB Compensation Control */ - pci_write_config8(dev, 0xB9, 0x84); - reg = pci_read_config8(dev, 0xB8); - reg |= 0x01; - pci_write_config8(dev, 0xB8, reg); - - pci_write_config8(dev, 0xBA, 0x6a); - pci_write_config8(dev, 0xBB, 0x01); - -#ifdef DEBUG_CN400 - /* Reconnect the VLink Before Continuing*/ - reg = pci_read_config8(dev, 0x47); - reg &= ~0x04; - pci_write_config8(dev, 0x47, reg); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif -} - -static const struct device_operations vlink_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vlink_init, - .ops_pci = 0, -}; - -static const struct pci_driver vlink_driver __pci_driver = { - .ops = &vlink_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_VLINK, -}; - -static void c3_host_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - -static const struct device_operations c3_host_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = c3_host_init, - .ops_pci = 0, -}; - -static const struct pci_driver c3_host_driver __pci_driver = { - .ops = &c3_host_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_HOST, -}; - - -static void c3_err_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - -static const struct device_operations c3_err_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = c3_err_init, - .ops_pci = 0, -}; - -static const struct pci_driver c3_err_driver __pci_driver = { - .ops = &c3_err_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_ERR, -}; - -static void cn400_pm_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - -static const struct device_operations cn400_pm_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cn400_pm_init, - .ops_pci = 0, -}; - -static const struct pci_driver cn400_pm_driver __pci_driver = { - .ops = &c3_err_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_CN400_PM, -}; |