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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-22 19:57:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-03 13:28:34 +0000 |
| commit | 9c8895fd889b01fe71bb296e2566b96a9542b303 (patch) | |
| tree | 6756713e43a31ef48df442780e7ea524002bd335 /src/northbridge | |
| parent | fa1f7216ce2105aab79ee91cb3f8c8e879ded341 (diff) | |
| download | coreboot-9c8895fd889b01fe71bb296e2566b96a9542b303.tar.gz coreboot-9c8895fd889b01fe71bb296e2566b96a9542b303.tar.bz2 coreboot-9c8895fd889b01fe71bb296e2566b96a9542b303.zip | |
nb/intel/sandybridge: Remove variable set but not used
Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32938
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 53f28c6cd663..4974173ef129 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1452,9 +1452,8 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) int lane; FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); @@ -2026,9 +2025,8 @@ int write_training(ramctr_timing * ctrl) MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - tmp = MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ @@ -2373,9 +2371,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2454,8 +2451,7 @@ int discover_edges(ramctr_timing *ctrl) fill_pattern0(ctrl, channel, 0, 0); MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2655,10 +2651,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2703,8 +2698,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, wait_428c(channel); FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x4340 + + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } |