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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-10 15:50:04 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-13 12:46:18 +0000 |
| commit | 2882253237f254d5f78b7531ef3cefb974cd4bbb (patch) | |
| tree | 91216e1814cff2806f15c503155d3ad3446cc48e /src/northbridge | |
| parent | b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (diff) | |
| download | coreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.gz coreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.bz2 coreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.zip | |
nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
existing bootblock_mainboard_early_init().
Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/nehalem/Kconfig | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/bootblock.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/romstage.c | 5 |
4 files changed, 11 insertions, 9 deletions
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3adf6987bf81..ba9616d31b44 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP + select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_NEHALEM @@ -48,9 +49,12 @@ config DCACHE_RAM_SIZE hex default 0x10000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/nehalem/bootblock.c" +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. config MRC_CACHE_SIZE hex diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 3b12bb58546c..225f0ce812d9 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index f96ff56a565f..46cdef0c474a 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -12,8 +12,9 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 54766de0e702..81883038778d 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -45,11 +45,6 @@ void mainboard_romstage_entry(void) /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - pch_pre_console_init(); - - /* Initialize console device(s) */ - console_init(); - early_pch_init(); /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ |