move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.

this patch also slightly changes it so we have a single cache_as_ram.inc which
requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
worse, a lot of cruft hacked right into romstage.c like on tyan s2735)

Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 1 insertions, 100 deletions

diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 77ee43830d67..9fac9a311074 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -300,7 +300,7 @@ void EmbedComInit()
 
 /* cache_as_ram.inc jump to here
 */
-void stage1_main(unsigned long bist)
+void main(unsigned long bist)
 {
 	unsigned cpu_reset = 0;
 	u16 boot_mode;
@@ -556,103 +556,4 @@ g)      Rx73h = 32h
 		);*/
 	}
 #endif
-/*
-the following code is  copied from src/mainboard/tyan/s2735/romstage.c
-Only the code around CLEAR_FIRST_1M_RAM is changed.
-I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c"
-the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, 
-and cpu/x86/car/cache_as_ram_post.c  do not cache my $CONFIG_XIP_ROM_BASE+SIZE area.
-
-So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version
-*/
-#if 1
-	{
-		/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-		unsigned v_esp;
-		__asm__ volatile ("movl   %%esp, %0\n\t":"=a" (v_esp)
-		    );
-#if CONFIG_USE_PRINTK_IN_CAR
-		printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
-#else
-		print_debug("v_esp=");
-		print_debug_hex32(v_esp);
-		print_debug("\n");
-#endif
-	}
-
-#endif
-#if 1
-
-      cpu_reset_x:
-// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy 
-//stack
-	cpu_reset = 0;
-#if CONFIG_USE_PRINTK_IN_CAR
-	printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
-#else
-	print_debug("cpu_reset = ");
-	print_debug_hex32(cpu_reset);
-	print_debug("\n");
-#endif
-
-	if (cpu_reset == 0) {
-		print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-	__asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset)
-	    );
-
-
-/* cancel these lines, CLEAR_FIRST_1M_RAM cause the cpu/x86/car/cache_as_ram_post.c stop at somewhere
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/via/car/cache_as_ram_post.c"	
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/via/car/cache_as_ram_post.c"
-	}
-*/
-#include "cpu/via/car/cache_as_ram_post.c"
-//#include "cpu/x86/car/cache_as_ram_post.c"    
-	__asm__ volatile (
-				 /* set new esp *//* before CONFIG_RAMBASE */
-				 "subl   %0, %%ebp\n\t"
-				 "subl   %0, %%esp\n\t"::
-				 "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) -
-				      CONFIG_RAMBASE)
-	    );
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset)
-		    );
-
-		/* We can not go back any more, we lost old stack data in cache as ram */
-		if (new_cpu_reset == 0) {
-			print_debug("Use Ram as Stack now - done\n");
-		} else {
-			print_debug("Use Ram as Stack now - \n");
-		}
-#if CONFIG_USE_PRINTK_IN_CAR
-		printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
-#else
-		print_debug("new_cpu_reset = ");
-		print_debug_hex32(new_cpu_reset);
-		print_debug("\n");
-#endif
-		/*copy and execute coreboot_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\n");
-
 }