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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-02-23 14:03:43 +0530
committerWerner Zeh <werner.zeh@siemens.com>2021-05-10 06:40:37 +0000
commit91b2024bae0b35967b07eb30084c3f55fe5aaa4b (patch)
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parent4b97a134857f98c4c0378ab0118b75b5b6a482dc (diff)
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soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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