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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-10-05 21:48:07 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 20:19:03 +0000 |
| commit | c6f029cbccc7a1ae4f7463e5d519a32f0df100dd (patch) | |
| tree | b04ff319b00005b453621b492a24e4a5e3476f64 /src/soc/amd/cezanne/chipset.cb | |
| parent | fd2bb9b6bc06515f2a42a8575812271765f73313 (diff) | |
| download | coreboot-c6f029cbccc7a1ae4f7463e5d519a32f0df100dd.tar.gz coreboot-c6f029cbccc7a1ae4f7463e5d519a32f0df100dd.tar.bz2 coreboot-c6f029cbccc7a1ae4f7463e5d519a32f0df100dd.zip | |
soc/amd/*: Hook up LPC ops in devicetree
This removes the need for a PCI driver.
Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne/chipset.cb')
| -rw-r--r-- | src/soc/amd/cezanne/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index f1cc81a44e93..3a6ea4219e05 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -95,7 +95,7 @@ chip soc/amd/cezanne end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function - device pci 14.3 alias lpc_bridge on end + device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end device pci 18.0 alias data_fabric_0 on ops cezanne_data_fabric_ops end device pci 18.1 alias data_fabric_1 on ops cezanne_data_fabric_ops end |