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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-04 21:51:43 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-09 18:11:21 +0000 |
| commit | 1ed5a63c8c8b2680ee4371427aa6482a59777326 (patch) | |
| tree | 256439f0377389ea21dcb71002d7c289db8bcdc9 /src/soc/amd/cezanne/fsp_m_params.c | |
| parent | 6d9a0eab702213514cc7fba8d0a71c39b2a14585 (diff) | |
| download | coreboot-1ed5a63c8c8b2680ee4371427aa6482a59777326.tar.gz coreboot-1ed5a63c8c8b2680ee4371427aa6482a59777326.tar.bz2 coreboot-1ed5a63c8c8b2680ee4371427aa6482a59777326.zip | |
soc/amd/cezanne: add GNB IOAPIC support
To configure and enable the IOAPIC in the graphics and northbridge (GNB)
container, FSP needs to write an undocumented register, so pass the GNB
IOAPIC MMIO base address to make it show up at that address.
BUG=b:187083211
TEST=Boot guybrush and see IO-APIC initialized
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/fsp_m_params.c')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ffa141c..4aff7e09bb6a 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/apob_cache.h> +#include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <assert.h> #include <console/uart.h> @@ -50,6 +51,13 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); } +static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -129,4 +137,5 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) config->telemetry_vddcrsocoffset; fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); } |