diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-18 19:06:50 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-20 20:43:17 +0000 |
| commit | 02b61ae9c034ed80cb726df44210cc7d20898b6f (patch) | |
| tree | 9d9b634a5318e0487564976a9805afc2ac49f2a5 /src/soc/amd/common/block/psp | |
| parent | f7d86f21e12aa3a368aa87aa4a1406e7c38e07b0 (diff) | |
| download | coreboot-02b61ae9c034ed80cb726df44210cc7d20898b6f.tar.gz coreboot-02b61ae9c034ed80cb726df44210cc7d20898b6f.tar.bz2 coreboot-02b61ae9c034ed80cb726df44210cc7d20898b6f.zip | |
soc/amd/stoneyridge: move early I2C init to early_fch.c
Since the I2C controller is part of the FCH, move the early
initialization from bootblock.c to early_fch.c which also matches what
the newer AMD SoCs do.
TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions
appear to work properly
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/psp')
0 files changed, 0 insertions, 0 deletions